ADRF6821 datasheet(53/61 Pages) AD

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Data Sheet

ADRF6821

Rev. A | Page 53 of 61

Dis able VCO Autom atic Lev el Control

(ALC) and Auto m atic Fre q ue nc y Co ntro l

(AFC) Calib ratio n

1: Pow er Up Sy nthes iz er.

0: Pow er Dow n Sy nthes iz er.

[ 7 ] RES ERV ED

[ 5 :0 ] RES ERV ED

[ 6 ] D IS ABLE_CAL ( R/W )

Table 67. Bit Descriptions for VCO_FSM

Bits

Bit Name

Settings

Description

Reset

Access

RESERVED

Reserved.

0x0

DISABLE_CAL

Disable VCO Automatic Level Control (ALC) and Automatic Frequency Control

(AFC) Calibration. The PLL does not reset the calibration machine or trigger a new

calibration if set to 1 on a frequency hop to maintain ALC and capacitor positions.

0x0

R/W

Power-Down Synthesizer.

Power-Up Synthesizer.

[5:0]

RESERVED

Reserved.

0x0

R/W

Address: 0x122A, Reset: 0x02, Name: SD_CTRL

Sig m a-De lta Enab le w ith FRAC = 0

Loss of Lock (LOL) Enabled

Sig m a-De lta Enab le , Outp ut Off

[ 7 :6 ] RES ERV ED

[ 0 ] RES ERV ED

[ 5 ] S D _EN _FRAC0 ( R/W )

[ 1 ] S D _S M _2 ( R/W )

[ 4 ] S D _EN _O UT _O FF ( R/W )

[ 3 :2 ] RES ERV ED

Table 68. Bit Descriptions for SD_CTRL

Bits

Bit Name

Settings

Description

Reset

Access

[7:6]

RESERVED

Reserved.

0x0

R/W

SD_EN_FRAC0

Sigma-Delta Enable with FRAC = 0. The DSM normally recognizes a FRAC value

of all 0, and disables itself. Setting this mode can keep the DSM running even

when a zero FRAC is presented.

0x0

R/W

SD_EN_OUT_OFF

Sigma-Delta Enable, Output Off. Keeps the DSM core enabled and clocking but

ignores the output of the DSM and instead multiplexes the N divider setpoint

from the double buffer data directly.

0x0

R/W

[3:2]

RESERVED

Reserved.

0x0

SD_SM_2

Loss of Lock (LOL) Enabled. Enables the CSP/LOL circuit. Recommend Reserved 1.

0x1

R/W

RESERVED

Reserved.

0x0

R/W

Address: 0x122C, Reset: 0x03, Name: MULTI_FUNC_SYNTH_CTRL_022C

Charge Pum p Tristate

3: Charge Pum p Tristate Mode 3.

2: Charge Pum p Tristate Mode 2.

1: Charge Pum p Tristate Mode 1.

0: Charge Pum p Tristate Mode 0.

[7:2] RESERVED

[1:0] CP_HIZ (R/W)

Table 69. Bit Descriptions for MULTI_FUNC_SYNTH_CTRL_022C

Bits

Bit Name

Settings

Description

Reset

Access

[7:2]

RESERVED

Reserved

0x0

[1:0]

CP_HIZ

Charge Pump Tristate

0x3

R/W

Charge Pump Tristate Mode 0

Charge Pump Tristate Mode 1

Charge Pump Tristate Mode 2

Charge Pump Tristate Mode 3

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