ADRF6821 datasheet(46/61 Pages) AD

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ADRF6821

Data Sheet

Rev. A | Page 46 of 61

Address: 0x0090, Reset: 0x00, Name: EN_LO_DIVIDER_CTRL

LO Path Bias Curre nt Enab le (0 :o ff 1:o n)

Bo th Paths

Q Channel LO PreDriv er Enable (0:off

1:o n)

LO Div ider Path Buffer Enable (0:off

1:o n)

I Channel LO PreDriv er Enable (0:off

1:o n)

LO Div ider Path I/Q Div ider Enable (0:off

1:o n)

Q Channe l LO Driv e r Enab le (0 :o ff 1:o n)

I Channe l LO Driv e r Enab le (0 :o ff 1:o n)

[ 7 ] RES ERV ED

[ 0 ] EN _IBIAS GEN ( R/W )

[ 6 ] EN _LO D RV _P RED RV Q ( R/W )

[ 1 ] EN _D IV P AT H _BUF ( R/W )

[ 5 ] EN _LO D RV _P RED RV I ( R/W )

[ 2 ] EN_DIV P AT H_Q UADDIV ( R/W )

[ 4 ] EN _LO D RV _D RV Q ( R/W )

[ 3 ] EN _LO D RV _D RV I ( R/W )

Table 44. Bit Descriptions for EN_LO_DIVIDER_CTRL

Bits

Bit Name

Settings

Description

Reset

Access

RESERVED

Reserved.

0x0

EN_LODRV_PREDRVQ

Q Channel LO Predriver Enable (0: off and 1: on). LO path mixer predriver

enable. This must be enabled whenever LO path is enabled.

0x0

R/W

EN_LODRV_PREDRVI

I Channel LO Predriver Enable (0: off and 1: on). LO path mixer predriver

enable. This must be enabled whenever LO path is enabled.

0x0

R/W

EN_LODRV_DRVQ

Q Channel LO Driver Enable (0: off and 1: on). LO path mixer driver enable.

This must be enabled whenever LO path is enabled.

0x0

R/W

EN_LODRV_DRVI

I Channel LO Driver Enable (0: off and 1: on). LO path mixer driver enable.

This must be enabled whenever LO path is enabled.

0x0

R/W

EN_DIVPATH_QUADDIV

LO Divider Path I/Q Divider Enable (0: off and 1: on). Blocks required to be

enabled in this path are: EN_DIVPATH_BUF, EN_LODRVR_DRVx,

EN_LODRVR_PREDRVRx, EN_IBIASGEN, EN_ICMLOBIAS_x,

CODE_MIXER_DRVR.

0x0

R/W

EN_DIVPATH_BUF

LO Divider Path Buffer Enable (0: off and 1: on). Blocks required to be

enabled in this path are: EN_DIVPATH_QUADDIV, EN_LODRVR_DRVx,

EN_LODRVR_PREDRVRx, EN_IBIASGEN, EN_ICMLOBIAS_x,

CODE_MIXER_DRVR.

0x0

R/W

EN_IBIASGEN

LO Path Bias Current Enable (0: off and 1) Both Paths.

0x0

R/W

Address: 0x0092, Reset: 0x00, Name: LO_PHASE_ADJ

Q Channe l LO Phas e Ad jus tm e nt

I Channe l LO Phas e Ad jus tm e nt

[ 7 : 4 ] T RM _LO D RV _CAP Q ( R/W )

[ 3 : 0 ] T RM _LO D RV _CAP I ( R/W )

Table 45. Bit Descriptions for LO_PHASE_ADJ

Bits

Bit Name

Settings

Description

Reset

Access

[7:4]

TRM_LODRV_CAPQ

Q Channel LO Phase Adjustment. LO Quadrature Phase Adjust. Valid range is

from 0x0 to 0xF. For no compensation or adjustment, both TRM_LODRV_CAPI

and TRM_LODRV_CAPQ must be set to the same value.

0x0

R/W

[3:0]

TRM_LODRV_CAPI

I Channel LO Phase Adjustment. LO Quadrature Phase Adjust. Valid range is

from 0x0 to 0xF. For no compensation or adjustment, both TRM_LODRV_CAPI

and TRM_LODRV_CAPQ must be set to the same value.

0x0

R/W

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