ADF4401ABCEZ datasheet(20/39 Pages) AD

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ADF4401A

Data Sheet

Rev. 0 | Page 20 of 39

From Equation 8,

fPFD = (122.88 MHz × (1/2) = 61.44 MHz

(17)

2112.8 MHz = 61.44 MHz × ((INT + (FRAC1 +

FRAC2/MOD2)/225))/2

(18)

where:

INT = 68.

FRAC1 = 26,039,637.

MOD2 = 1536.

FRAC2 = 512.

RF Divider = 2.

VCO CALIBRATION TIME

The VCO calibration settling time divides into a number of

settings. The total lock time for changing frequencies is the sum

of the four separate times: synthesizer lock, VCO band selection,

automatic level calibration (ALC), and calibration PLL settling

time.

Synthesizer Lock

The synthesizer lock timeout ensures that the VCO calibration

DAC, which forces the VCO tune voltage (VTUNE), has settled

to a steady value for the band select circuitry. SYNTH_LOCK_

TIMEOUT and timeout select the length of time the DAC is

allowed to settle to the final voltage before the VCO calibration

process continues to the next phase (VCO band selection).

The PFD frequency is the clock for this logic, and the duration

is set using the following equation:

×+

1024

PFD

SYNTH LOCK TIMEOUT

timeout

(19)

where:

SYNTH_LOCK_TIMEOUT is programmed in REG0033.

Timeout is programmed in REG0031 and REG0032.

The calculated time must be greater than or equal to 20 µs.

For the SYNTH_LOCK_TIMEOUT bit, the minimum value is

2 and the maximum value is 31. For the timeout bit, the

minimum value is 2 and the maximum value is 1023.

VCO Band Selection

VCO_BAND_DIV (programmed in the REG0030 register) and

the fPFD are used to generate the VCO band selection clock as

follows:

PFD

BSC

VCO BAND DIV

(20)

where fBSC is the band select clock frequency.

The calculated frequency must be less than 2.4 MHz.

16 clock cycles are required for one VCO core and band calibration

step, and the total band selection process takes 11 steps, resulting

in the following equation:

× 16

PFD

VCO BAND DIV

(21)

The minimum value for VCO_BAND_DIV is 1 and the

maximum value is 255.

Automatic Level Calibration

Use the ALC function to choose the correct bias current in the

ADF4401A VCO core. The duration required for the VCO bias

voltage to settle for each step is set by the following equation:

×+

1024

PFD

VCO ALC TIMEOUT

timeout

(22)

where

VCO_ALC_TIMEOUT and timeout are programmed in the

REG0034, REG0032, and REG0031 registers.

The calculated time must be greater than or equal to 50 µs.

The total ALC takes 63 steps, as shown in the following

equation:

×+

1024

PFD

VCO ALC TIMEOUT

timeout

(23)

The minimum value for VCO_ALC_TIMEOUT is 2, and the

maximum value is 31.

Calibration PLL Settling Time

The time taken for the loop to settle is inversely proportional to

the low-pass filter bandwidth. The settling time is accurately

modeled in the ADIsimPLL design tool.

Calibration Lock Time, a Worked Example

Assume that fPFD = 61.44 MHz,

VCO_BAND_DIV = Ceiling(fPFD/2,400,000) = 26

(24)

where Ceiling() rounds up to the nearest integer.

SYNTH_LOCK_TIMEOUT × 1024 + timeout > 1228.8

(25)

VCO_ALC_TIMEOUT × 1024 + timeout > 3072

(26)

There are several suitable values that meet these criteria. By

considering the minimum specifications, the following values

are the most suitable:

•

SYNTH_LOCK_TIMEOUT = 2 (minimum value)

•

VCO_ALC_TIMEOUT = 3

•

Timeout = 2

Much faster lock times than those detailed in this data sheet are

possible by bypassing the calibration processes. See the AN-

2005 Application Note for more information.

LOCAL OSCILLATOR (LO_IN)

The selection of an external LO to the ADF4401A is of critical

importance. Because the divider function has been replaced by a

mixer, the phase noise of the external LO modulates the carrier

frequency inside the PLL loop bandwidth and dominates the

measured phase noise. For this reason, only the highest

performance LO sources, such as voltage controlled surface

acoustic wave (SAW) oscillators (VCSOs), comb generators, and

dielectric resonator oscillators (DROs), are recommended.

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