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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ADF4401ABCEZ датащи(PDF) 6 Page - Analog Devices |
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ADF4401ABCEZ датащи(HTML) 6 Page - Analog Devices |
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6 / 39 page  ADF4401A Data Sheet Rev. 0 | Page 6 of 39 TIMING CHARACTERISTICS See Figure 2, Figure 3, and Figure 4. Table 2. SPI Timing Parameter Min Typ Max Unit Description fSCLK 50 MHz SCLK frequency tSCLK 20 ns SCLK period tHIGH 10 ns SCLK pulse width high tLOW 10 ns SCLK pulse width low tDS 5 ns SDIO setup time tDH 5 ns SDIO hold time tACCESS 10 ns SCLK falling edge to SDIO valid propagation delay tZ 10 ns CS rising edge to SDIO high-z tS 5 ns CS falling edge to SCLK rising edge setup time tH 5 ns SCLK rising edge to CS rising edge hold time Timing Diagrams SCLK SDIO R/W A1 A0 D7 D61 D1 D0N DATA TRANSFER CYCLE INSTRUCTION CYCLE CS A14 A13 SCLK SDIO R/W A1 A0 D7 D61 D1 D0N DATA TRANSFER CYCLE INSTRUCTION CYCLE CS A14 A2 Figure 2. SPI Timing, MSB First (Upper) and LSB First (Lower) D7 D6 A0 D1 A14 tS SCLK SDIO tSCLK tLOW tHIGH tDS tDH R/W D0 tH A13 CS Figure 3. SPI Write Operation Timing D7 D6 A0 D1 A14 tS SCLK SDIO tSCLK tLOW tHIGH tDS tDH R/W D0 tZ A2 A1 tACCESS CS Figure 4. SPI Read Operation Timing A14 R/W A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 DON’T CARE DON’T CARE DON’T CARE DON’T CARE SCLK SDIO CS 16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N – 1) DATA REGISTER (N – ...) DATA Figure 5. 3-Wire, MSB First, Descending Data, Streaming |
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