ADF4401ABCEZ datasheet(33/39 Pages) AD

33 / 39 page

Data Sheet

ADF4401A

Rev. 0 | Page 33 of 39

Bit(s)

Bit Name

Description

Default

Access

ADC_FAST_CONV

ADC Fast Conversion.

0x0

R/W

0: disabled.

1: enabled.

ADC_CTS_CONV

ADC Continuous Conversion.

0x0

R/W

0: disabled.

1: enabled.

ADC_CONVERSION

Enables ADC Conversion.

0x0

R/W

0: no ADC conversion.

1: perform ADC conversion on REG0000 write if ADC is enabled.

ADC_ENABLE

ADC Enable.

0x1

R/W

0: disabled.

1: enabled.

[1:0]

TIMEOUT[9:8]

Used as Part of the ALC Wait Time and Synthetic Lock Time. See the VCO Calibration

Time section for details.

0x0

R/W

Address: 0x33, Default: 0x0C, Name: REG0033

Part of VCO Calibration Routine.

[7:5] RESERVED

[4:0] SYNTH_LOCK_TIMEOUT (R/W)

Table 37. Bit Descriptions for REG0033

Bit(s)

Bit Name

Description

Default

Access

[7:5]

RESERVED

Reserved.

0x0

[4:0]

SYNTH_LOCK_TIMEOUT

Part of VCO Calibration Routine. See the VCO Calibration Time section for

details.

0xC

R/W

Address: 0x34, Default: 0x9E, Name: REG0034

Res erved.

Wait Tim e for ALC Loop to Settle.

[7:5] VCO_FSM_TEST_MODES (R/W)

[4:0] VCO_ALC_TIMEOUT (R/W)

Table 38. Bit Descriptions for REG0034

Bit(s)

Bit Name

Description

Default

Access

[7:5]

VCO_FSM_TEST_MODES

Reserved.

0x4

R/W

[4:0]

VCO_ALC_TIMEOUT

Wait Time for ALC Loop to Settle. See the VCO Calibration Time section for

details.

0x1E

R/W

Address: 0x35, Default: 0x4C, Name: REG0035

ADC Clock Divider.

[7:0] ADC_CLK_DIVIDER (R/W)

Table 39. Bit Descriptions for REG0035

Bit(s)

Bit Name

Description

Default

Access

[7:0]

ADC_CLK_DIVIDER

ADC Clock Divider. ADC clock = fPFD/((ADC_CLK_DIVIDER × 4) + 2). Target 100 kHz for

ADC clock Refer to AN-2005 for more details.

0x4C

R/W

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