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ADF4401ABCEZ датащи(PDF) 26 Page - Analog Devices

номер детали ADF4401ABCEZ
подробное описание детали  Translation Loop, PLL, VCO Module
PDF  39 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

ADF4401ABCEZ датащи(HTML) 26 Page - Analog Devices

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ADF4401A
Data Sheet
Rev. 0 | Page 26 of 39
Address: 0x1A, Default: 0x03, Name: REG001A
14-Bit MOD2 Value.
0
1
1
1
2
0
3
0
4
0
5
0
6
0
7
0
[7:6] RESERVED
[5:0] MOD2WORD[13:8] (R/W)
Table 20. Bit Descriptions for REG001A
Bit(s)
Bit Name
Description
Default
Access
[7:6]
RESERVED
Reserved.
0x0
R
[5:0]
MOD2WORD[13:8]
14-Bit MOD2 Value. Sets the MOD2 value.
0x3
R/W
Address: 0x1E, Default: 0x48, Name: REG001E
Charge Pum p Current Setting.
Counter Res et.
Internal Phas e Detector Polarity.
Power-Down.
0
0
1
0
2
0
3
1
4
0
5
0
6
1
7
0
[7:4] CP_CURRENT (R/W)
[0] CNTR_RESET (R/W)
[3] PD_POL (R/W)
[1] RESERVED
[2] PD (R/W)
Table 21. Bit Descriptions for REG001E
Bit(s)
Bit Name
Description
Default
Access
[7:4]
CP_CURRENT
Charge Pump Current Setting. Sets the charge pump current. Set the CP_CURRENT bits to the
charge pump current that the loop filter is designed for.
0x4
R/W
0: 0.35 mA.
1: 0.70 mA.
10: 1.05 mA.
11: 1.4 mA.
100: 1.75 mA.
101: 2.1 mA.
110: 2.45 mA.
111: 2.8 mA.
1000: 3.15 mA.
1001: 3.5 mA.
1010: 3.85 mA.
1011: 4.2 mA.
1100: 4.55 mA.
1101: 4.9 mA.
1110: 5.25 mA.
1111: 5.6 mA.
3
PD_POL
Internal Phase Detector Polarity. If using a noninverting loop filter, set phase detector polarity
to positive. If using an inverting loop filter, set phase detector polarity to negative.
0x1
R/W
0: negative phase detector polarity.
1: positive phase detector polarity.
2
PD
Power-Down. Setting to 1 powers down all internal PLL blocks of the VCO/PLL. The VCO and
multipliers remain powered up. The registers do not lose their values. After bringing the
ADF4401A back to calibration mode (setting to 0) a write to REG0010 is required to relock the
calibration loop.
0x0
R/W
0: calibration mode.
1: translation loop mode.
1
RESERVED
Reserved.
0x0
R
0
CNTR_RESET
Counter Reset. Setting to 1 holds the N divider and R counter in reset. There are no signals
entering the PFD.
0x0
R/W
0: normal operation.
1: counter reset.



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