ADF4401ABCEZ datasheet(9/39 Pages) AD

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Data Sheet

ADF4401A

Rev. 0 | Page 9 of 39

Pin No.

Mnemonic

Description

IFOUT

Amplified Downconverted Output from the Mixer. Connect the IFOUT pin to an

external phase detector or PFD.

34, 35

VCC_IF1

5 V Supply to the IF Amplifier Connected to the Mixer IF Output.

LO_IN

External RF Input to the Downconversion Mixer. Power can range from −3 dBm to

+3 dBm. Take care to isolate LO_IN from the VCO circuitry and RF output. The LO_IN

pin is matched internally to 50 Ω and must be ac-coupled.

X2_EN

Mixer Doubler Enable. A logic high to X2_EN doubles the LO_IN frequency to the

downconversion mixer.

53, 54

VCC_MIX

Power Supply for Downconversion Mixer. The voltage on the VCC_MIX pin ranges

from 3.15 V to 3.45 V. VCC_MIX must have the same value as AVDD, nominally 3.3 V.

VCC_RF

5 V Supply to the RF Amplifier Connected to the Mixer RF Input.

VRF_INT

Power Supply for PLL and VCO Auxiliary RF Output Driving the Mixer. The voltage on

the VRF_INT pin ranges from 3.15 V to 3.45 V. VRF_INT must have the same value as

AVDD, nominally 3.3 V.

RF8P

RF Output. The output level is programmable. The VCO fundamental output or a

divided down version is available. Pull-up inductors to VRF_OUT increase the output

power level.

RF8N

Complementary RF Output. The output level is programmable. The VCO fundamental

output or a divided down version is available. Pull-up inductors to VRF_OUT increase

the output power level.

70, 71

VRF_OUT

Power Supply for PLL and VCO Main RF Output. The voltage on the VRF_OUT pin

ranges from 3.15 V to 3.45 V. VRF_OUT must have the same value as AVDD, nominally

3.3 V.

VCC_DIV

Power Supply for the VCO Output Stage and Divider. The voltage on the VCC_DIV pin

must have the same value as AVDD, nominally 3.3 V.

VCC_NDIV

N Divider Power Supply. The voltage on the VCC_NDIV pin must have the same value

as AVDD, nominally 3.3 V.

VCC_REG

Regulator Input for 1.8 V Digital Logic. The voltage on the VCC_REG pin must have the

same value as AVDD, nominally 3.3 V.

Chip Select, CMOS Input. When CS goes high, the data stored in the shift register is

loaded into the register that is selected by the address bits.

SDIO

Serial Data Input Output. This input is a high impedance CMOS input.

SCLK

Serial Clock Input. Data is clocked into the 24-bit shift register on the clock rising edge.

This input is a high impedance CMOS input.

Chip Enable. Connect to 3.3 V or AVDD. A logic low on the CE pin shuts down the PLL

and VCO circuitry.

EPAD

Exposed Pad. The land grid array (LGA) has an exposed pad that must be soldered to a

metal plate on the PCB for mechanical reasons and to GND.

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