ADF4401ABCEZ datasheet(16/39 Pages) AD

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ADF4401A

Data Sheet

Rev. 0 | Page 16 of 39

DOUBLE BUFFERS

The FRAC1 value, FRAC2 value, MOD2 value, reference doubler,

reference divide by 2 (RDIV2), R counter value, and charge

pump current setting are double buffered in the ADF4401A.

Two events must occur before the ADF4401A uses a new value

for any of the double buffered settings. First, the new value must

latch into the device by writing to the appropriate register, and

second, a new write to the REG0010 register must be

performed.

For example, to ensure that the MOD2 value loads correctly,

the REG0010 register must be written to every time the MOD2

value updates.

VCO

The VCO core in the ADF4401A consists of four separate VCO

cores: Core A, Core B, Core C, and Core D. Each core uses 256

overlapping bands, which allows the device to cover a wide

frequency range with small VCO sensitivity (KV) and optimal

phase noise and spurious performance.

The proper VCO and band are chosen automatically by the

VCO and band select logic whenever the REG0010 register is

updated and automatic calibration is enabled. The VTUNE pin is

disconnected from the output of the loop filter and is connected

to an internal reference voltage.

The R counter output is used as the clock for the band select

logic. After band selection, normal PLL action resumes. The

nominal value of KV along with an average value are shown in

Figure 30 when the N divider is driven from the VCO output,

or the KV value is divided by D. D is the output divider value if

the N divider is driven from the RF output divider.

The VCO shows the variation of KV as the tuning voltage,

VTUNE, varies both within the band and from band to band.

For wideband applications covering a wide frequency range

(and changing output dividers), a value of 80 MHz/V provides the

most accurate KV, because this value is closest to the average value.

150

100

110

120

130

140

4.0

8.0

7.5

7.0

6.5

6.0

5.5

5.0

4.5

FREQUENCY (GHz)

Figure 30. VCO Sensitivity, KV vs. Frequency

OUTPUT STAGE

The RF8P and RF8N pins of the ADF4401A connect to the

collectors of a bipolar negative positive negative (NPN) differential

pair driven by buffered outputs of the VCO, as shown in Figure 31.

The ADF4401A contains internal 50 Ω resistors connected to

the VRF_OUT pins. To optimize the power dissipation vs. the

output power requirements, the tail current of the differential

pair is programmable using REG0025, Bits[1:0]. Four current

levels can be set. These levels provide approximate output power

levels of −4 dBm, −1 dBm, 2 dBm, and 5 dBm. Levels of −4 dBm

and −1 dBm can be achieved by ac coupling into a 50 Ω load. The

2 dBm and 5 dBm levels must be used with an external shunt

inductor to VRF_OUT, or else the output stage may compress.

An inductor has a narrower operating frequency than a 50 Ω

resistor. For accurate power levels, refer to the Typical

Performance Characteristics section. Add an external shunt

inductor to provide higher power levels, which is less wideband

than the internal bias only. Terminate the unused complementary

output with a circuit similar to the used output.

VCO

RF8P

RF8N

VRF_OUT

50Ω

BUFFER,

DIVIDE BY

1, 2, 4, 8,

16, 32, 64

Figure 31. Output Stage

SPI

The SPI of the ADF4401A allows the user to configure the device

as required via a 3-wire or 4-wire SPI port. This interface provides

users with added flexibility and customization. The SPI consists

of four control lines: SCLK, SDIO, CS, and MUXOUT.

MUXOUT is the serial data output in 4-wire SPI mode. The

timing requirements for the SPI port are detailed in Table 2.

The SPI protocol consists of a read and write bit and 15 register

address bits, followed by eight data bits. Both the address and

data fields are organized with the MSB first and end with the

LSB by default. Figure 3 and Figure 4 show the timing diagrams

for SPI writes and reads, respectively. The significant bit order

can be changed via the REG0000 register, Bit 1 (LSB_FIRST)

setting, and the related timing diagram is shown in Figure 2.

The ADF4401A input logic level for the write cycle is compatible

with a 1.8 V logic level. On a read cycle, both the SDIO and

MUXOUT pins are configurable for 1.8 V (default) or 3.3 V output

levels by the LEV_SEL bit setting.

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