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ADF4401ABCEZ датащи(PDF) 28 Page - Analog Devices

номер детали ADF4401ABCEZ
подробное описание детали  Translation Loop, PLL, VCO Module
PDF  39 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

ADF4401ABCEZ датащи(HTML) 28 Page - Analog Devices

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ADF4401A
Data Sheet
Rev. 0 | Page 28 of 39
Address: 0x22, Default: 0x00, Name: REG0022
Choos e Between Single-Ended or
Differential REFin.
RDIV2.
Reference Doubler.
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7] RESERVED
[3:0] RESERVED
[6] REFIN_MODE (R/W)
[4] RDIV2 (R/W)
[5] REF_DOUB (R/W)
Table 24. Bit Descriptions for REG0022
Bit(s)
Bit Name
Description
Default
Access
7
RESERVED
Reserved.
0x0
R
6
REFIN_MODE
Choose Between Single-Ended or Differential REFIN.
0x0
R/W
0: single-ended REFIN.
1: differential REFIN.
5
REF_DOUB
Reserved.
0x0
R/W
4
RDIV2
RDIV2. Controls the reference divide by 2 clock. This feature can be used to provide a 50%
duty cycle signal to the PFD.
0x0
R/W
0: RDIV2 disabled.
1: RDIV2 enabled.
[3:0]
RESERVED
Reserved.
0x0
R
Address: 0x24, Default: 0x80, Name: REG0024
Feedback.
Divis ion Selection.
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
1
[7] FB_SEL (R/W)
[3:0] RESERVED
[6:4] DIV_SEL (R/W)
Table 25. Bit Descriptions for REG0024
Bit(s)
Bit Name
Description
Default
Access
7
FB_SEL
Feedback.
0x1
R/W
0: divider feedback to N counter.
1: fundamental feedback to N counter.
[6:4]
DIV_SEL
Division Selection.
0x0
R/W
0: divide 1.
1: divide 2.
10: divide 4.
11: divide 8.
100: divide 16.
101: divide 32.
110: divide 64.
111: reserved.
[3:0]
RESERVED
Reserved.
0x0
R



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