ADF4401ABCEZ datasheet(29/39 Pages) AD

29 / 39 page

Data Sheet

ADF4401A

Rev. 0 | Page 29 of 39

Address: 0x25, Default: 0x07, Name: REG0025

Select Output Power Level.

Select if DIV_SEL is Double Buffered.

RFOUT Enable.

[7:6] RESERVED

[1:0] RF_OUT_POWER (R/W)

[5] RF_DIVSEL_DB (R/W)

[2] RF_EN (R/W)

[4:3] RESERVED

Table 26. Bit Descriptions for REG0025

Bit(s)

Bit Name

Description

Default

Access

[7:6]

RESERVED

Reserved.

0x0

RF_DIVSEL_DB

Select if DIV_SEL is Double Buffered.

0x0

R/W

[4:3]

RESERVED

Reserved.

0x0

R/W

RF_EN

RFOUT Enable.

0x1

R/W

0: RFOUT disabled.

1: RFOUT enabled.

[1:0]

RF_OUT_POWER

Select Output Power Level.

0x3

R/W

0: −4 dBm.

1: −1 dBm.

10: 2 dBm.

11: 5 dBm.

Address: 0x27, Default: 0xC5, Name: REG0027

Lock Detect Bias .

Lock Detect Precis ion.

[7:6] LD_BIAS (R/W)

[4:0] RESERVED

[5] LDP (R/W)

Table 27. Bit Descriptions for REG0027

Bit(s)

Bit Name

Description

Default

Access

[7:6]

LD_BIAS

Lock Detect Bias. The lock detector window size is set by adjusting the lock detector

bias in conjunction with the lock detector precision.

0x3

R/W

0: 5 ns lock detect delay if LDP = 0.

1: 6 ns.

10: 8 ns.

11: 12 ns lock detect delay (for large values of bleed)

LDP

Lock Detect Precision. Controls the sensitivity of the digital lock detector, depending on

INT or FRAC operation selected.

0x0

R/W

0: FRAC mode (5 ns).

1: INT mode (2.4 ns).

[4:0]

RESERVED

Reserved.

0x5

R/W

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