ADF4401ABCEZ datasheet(14/39 Pages) AD

14 / 39 page

ADF4401A

Data Sheet

Rev. 0 | Page 14 of 39

CIRCUIT DESCRIPTION

RF AMPLIFIER

The ADF4401A integrates an RF amplification stage between the

VCO output stage and the RF input of the mixer (see Figure 24).

The primary function of the RF amplifiers is to provide the

required drive level for the mixer and increase the effective

isolation of the LO on the RF output. A high-pass filter (HPF)

helps ensure spectral purity at the RF output and minimizes the

IF feedthrough to the RF output of the ADF4401A.

FROM VCO

MIXER LO

HPF

RF AMPLIFIER

Figure 24. RF Amplifiers

DOWNCONVERSION MIXER

DOWNCONVERSION

MIXER

LO_IN

FROM RF

AMPLIFIER

TO IF AMPLIFIER

×2

SW1

SW2

Figure 25. Downconversion Mixer

The mixer selected for the translation loop meets the following

requirements:

•

Operates in the required frequency range

•

High RF to LO isolation

•

Low noise figure

The LO_IN pin is connected to the mixer LO input. An

optional doubler on the LO path allows the user to select either

the LO_IN frequency or 2× LO_IN frequency to drive the

downconversion mixer. This doubler reduces the requirement

for external LO frequencies considerably.

IF AMPLIFIER

The ADF4401A integrates an IF amplification stage between the

output of the mixer and the IFOUT pin (see Figure 26). The IF

amplifier increases the LO to IF isolation of the mixer and

provides the required 15 dBm IFOUT drive level. Low-pass

filters (LPFs) placed before and after the IF amplifier remove

unwanted high frequency products from the mixer.

IF AMPLIFIER

IFOUT

MIXER IF

LPF

Figure 26. IF Amplifiers

CALIBRATION REFERENCE INPUT

Figure 27 shows the reference input stage of the calibration

PLL. This reference input assists the VCO in selecting the most

appropriate VCO band for optimal performance. When the

appropriate band is selected, the reference input can be shut down,

and the VCO can be locked with an external PFD circuit.

The reference input can accept both single-ended and differential

signals. Use the reference mode bit (REG0022, Bit 6) to select

the input mode. To use a differential signal on the reference input,

program REG0022, Bit 6 to 1. When using a differential signal,

SW1 and SW2 are open, SW3 and SW4 are closed, and the current

source that drives the differential pair of transistors switches on.

The differential signal is buffered and provided to an emitter

coupled logic (ECL) to the CMOS converter.

When a single-ended signal is used as the reference, connect

the reference signal to REFP and program REG0022, Bit 6 to 0.

When using a single-ended signal, SW1 and SW2 are closed,

SW3 and SW4 are open, and the current source that drives the

differential pair of transistors switches off.

50Ω

REFP

REFN

AVDD

BIAS

GENERATOR

BUFFER

85k

SW2

SW3

SW1

INPUT MODE

SW4

ECL TO CMOS

BUFFER

R COUNTER

MULTIPLEXER

Figure 27. Reference Input Stage, Differential Mode

RF N DIVIDER

The RF N divider allows a division ratio in the calibration PLL

feedback path. Determine the division ratio by the integer value

of N (INT), main fractional value (FRAC1), auxiliary fractional

value (FRAC2), and auxiliary modulus value (MOD2) that the

RF N divider comprises.

INT, FRAC1, FRAC2, MOD1, MOD2, and R Counter

Relationship

The INT, FRAC1, FRAC2, MOD1, and MOD2 values, in

conjunction with the R counter, make it possible to generate

output frequencies that are spaced by fractions of the PDF

frequency (fPFD). For more information, see the VCO

Calibration, a Worked Example section.

Calculate the VCO output frequency (fVCO_OUT) using the

following equation:

fVCO_OUT = fPFD × N

(1)

ADF4401ABCEZ датащи(PDF) 14 Page - Analog Devices

ADF4401ABCEZ датащи(HTML) 14 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

датащи скачать

ссылки URL