UPD360 datasheet(142/221 Pages) MICROCHIP

142 / 221 page

UPD360

DS00002084C-page 142

 2016-2017 Microchip Technology Inc.

EN_CRC_RCV_TMR

Enable CRCReceiveTimer.

0: CRCReceiveTimer disabled (default)

1: CRCReceiveTimer Enabled

This bit is used by software only when it is not using auto-retry mode.

When auto-retry is enabled (EN_AUTO_RSP_MODE in the TX Control Regis-

ter A (TX_CTL_A) is set and N_RETRY_CNT is non-zero) or when the trans-

mitter is set to wait for the GoodCRC message (EXPECT_GOODCRC is set

and N_RETRY_CNT is zero), the CRCReceiveTimer is automatically enabled

in hardware. If GoodCRC message is not received prior to timer expiration,

then an interrupt will be generated. CRC_RCV_TIMEOUT bit in the TX Inter-

rupt Status Register (TX_IRQ_STAT) will be set.

If auto-retry and wait for GoodCRC are disabled, the software can set this bit

to enable CRCReceiveTimer prior to starting transmission to help time tRe-

ceive. Once enabled, the timer will start automatically at the end of transmis-

sion; however, software must disable the timer when a GoodCRC message is

received. If not disabled, timer expiration will generate an interrupt.

Once expired, the CRCReceiveTimer remains expired until start of another

packet transmission when it reloads.

This timer can also be used for BIST transmissions as the BISTReceiveError-

Timer.

R/W

EN_SMBUS_MODE

Enable SMBus block read FIFO format.

0: First location in packet is status, second location is packet length

1: First location in packet is packet length + 1, second location is status

R/W

EN_CABLE_RESET

Enable Cable Reset Detection.

0: Cable Reset Detection (default)

1: Cable Reset Detection Enabled

R/W

Bits

Description

Type

Default

UPD360 датащи(PDF) 142 Page - Microchip Technology