PSD813F1 datasheet(34/110 Pages) STMICROELECTRONICS

34 / 110 page

PSD813F1

34/110

PLD’S

The PLDs bring programmable logic functionality

to the PSD. After specifying the logic for the PLDs

using the PSDabel tool in PSDsoft Express, the

logic is programmed into the device and available

upon power-up.

The PSD contains two PLDs: the Decode PLD

(DPLD), and the Complex PLD (CPLD). The PLDs

are briefly discussed in the next few paragraphs,

and in more detail in the sections entitled DE-

CODE PLD (DPLD) and COMPLEX PLD (CPLD).

Figure 15., page 35 shows the configuration of the

PLDs.

The DPLD performs address decoding for internal

and external components, such as memory, regis-

ters, and I/O port selects.

The CPLD can be used for logic functions, such as

loadable counters and shift registers, state ma-

chines, and encoding and decoding logic. These

logic functions can be constructed using the 16

Output macrocells (OMCs), 24 Input macrocells

(IMCs), and the AND array. The CPLD can also be

used to generate external chip selects.

The AND array is used to form product terms.

These product terms are specified using PSDabel.

An Input Bus consisting of 73 signals is connected

to the PLDs. The signals are shown in Table 13.

The Turbo Bit in PSD

The PLDs in the PSD can minimize power con-

sumption by switching off when inputs remain un-

changed for an extended time of about 70ns.

Setting the Turbo mode bit to off (Bit 3 of the

PMMR0 register) automatically places the PLDs

into standby if no inputs are changing. Turbo-off

mode increases propagation delays while reduc-

ing power consumption. See the section entitled

POWER MANAGEMENT, page 64, on how to set

the Turbo Bit.

Additionally, five bits are available in the PMMR2

the PLDs. This reduces power consumption and

can be used only when these MCU control signals

are not used in PLD logic equations.

The PLDs in the PSD can minimize power con-

sumption by switching off when inputs remain un-

changed for an extended time of about 70ns. Each

of the two PLDs has unique characteristics suited

for its applications. They are described in the fol-

lowing sections.

Table 13. DPLD and CPLD Inputs

Note: 1. The address inputs are A19-A4 in 80C51XA mode.

Input Source

Input Name

Number

Signals

MCU Address Bus1

A15-A0

MCU Control Signals

CNTL2-CNTL0

Reset

RST

Power-down

PDN

Port A Input

Macrocells

PA7-PA0

Port B Input

Macrocells

PB7-PB0

Port C Input

Macrocells

PC7-PC0

Port D Inputs

PD2-PD0

Page Register

PGR7-PGR0

Macrocell AB

Feedback

MCELLAB.FB7-

FB0

Macrocell BC

Feedback

MCELLBC.FB7-

FB0

EEPROM Program

Status Bit

Ready/Busy

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