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PSD813F1 датащи(PDF) 96 Page - STMicroelectronics

номер детали PSD813F1
подробное описание детали  Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
PDF  110 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PSD813F1 датащи(HTML) 96 Page - STMicroelectronics

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Figure 50. Peripheral I/O WRITE Timing
Table 65. Port A Peripheral Data Mode WRITE Timing (5V devices)
Note: 1. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode).
2. WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.
3. Any input used to select Port A Data Peripheral mode.
4. Data is already stable on Port A.
5. Data stable on ADIO pins to data on Port A.
Table 66. Port A Peripheral Data Mode WRITE Timing (3V devices)
Note: 1. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode) signals.
2. WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.
3. Any input used to select Port A Data Peripheral mode.
4. Data is already stable on Port A.
5. Data stable on ADIO pins to data on Port A.
Symbol
Parameter
Conditions
-90
-12
-15
Unit
Min
Max
Min
Max
Min
Max
tWLQV–PA
WR to Data Propagation Delay
(Note 2)
35
38
40
ns
tDVQV–PA
Data to Port A Data Propagation Delay
(Note 5)
30
35
38
ns
tWHQZ–PA
WR Invalid to Port A Tri-state
(Note 2)
25
30
33
ns
Symbol
Parameter
Conditions
-15
-20
Unit
MinMax
MinMax
tWLQV–PA
WR to Data Propagation Delay
(Note 2)
45
55
ns
tDVQV–PA
Data to Port A Data Propagation Delay
(Note 5)
40
45
ns
tWHQZ–PA
WR Invalid to Port A Tri-state
(Note 2)
33
35
ns
tDVQV (PA)
tWLQV
(PA)
tWHQZ (PA)
ADDRESS
DATA OUT
A / D BUS
WR
PORT A
DATA OUT
ALE /AS
AI02898



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