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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PSD813F1 датащи(PDF) 62 Page - STMicroelectronics |
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PSD813F1 датащи(HTML) 62 Page - STMicroelectronics |
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62 / 110 page  PSD813F1 62/110 Port D – Functionality and Structure Port D has three I/O pins. See Figure 31 and Fig- ure 32., page 63. This port does not support Ad- dress Out mode, and therefore no Control Register is required. Port D can be configured to perform one or more of the following functions: s MCU I/O Mode s CPLD Output – External Chip Select (ECS0- ECS2) s CPLD Input – direct input to the CPLD, no Input Macrocells (IMC) s Slew rate – pins can be set up for fast slew rate Port D pins can be configured in PSDsoft Express as input pins for other dedicated functions: s PD0 – ALE, as address strobe input s PD1 – CLKIN, as clock input to the macrocells flip-flops and APD counter s PD2 – CSI, as active Low chip select input. A High input will disable the Flash memory, EEPROM, SRAM and CSIOP. Figure 31. Port D Structure DATA OUT REG. DQ DQ WR WR ECS[ 2: 0] READ MUX P D B CPLD - INPUT DIR REG. DATA IN ENABLE PRODUCT TERM (.OE) OUTPUT SELECT OUTPUT MUX PORT D PIN DATA OUT AI02889 |
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