PSD813F1 datasheet(66/110 Pages) STMICROELECTRONICS

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PSD813F1

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For Users of the HC11 (or compatible)

The HC11 turns off its E clock when it sleeps.

Therefore, if you are using an HC11 (or compati-

ble) in your design, and you wish to use the Pow-

er-down mode, you must not connect the E clock

to CLKIN (PD1). You should instead connect an

independent clock signal to the CLKIN input

(PD1). The clock frequency must be less than 15

times the frequency of AS. The reason for this is

that if the frequency is greater than 15 times the

frequency of AS, the PSD will keep going into

Power-down mode.

Other Power Saving Options

The PSD offers other reduced power saving op-

tions that are independent of the Power-down

mode. Except for the SRAM Stand-by and Chip

Select Input (CSI, PD2) features, they are enabled

by setting bits in the PMMR0 and PMMR2 regis-

ters.

PLD Power Management

The power and speed of the PLDs are controlled

by the Turbo bit (bit 3) in the PMMR0. By setting

the bit to ‘1’, the Turbo mode is disabled and the

PLDs consume Zero Power current when the in-

puts are not switching for an extended time of

70ns. The propagation delay time will be in-

creased by 10ns after the Turbo bit is set to ‘1’

(turned off) when the inputs change at a composite

frequency of less than 15 MHz. When the Turbo bit

is set to a ‘0’ (turned on), the PLDs run at full power

and speed. The Turbo bit affects the PLD’s D.C.

power, AC power, and propagation delay.

Note: Blocking MCU control signals with PMMR2

bits can further reduce PLD AC power consump-

tion.

SRAM Standby Mode (Battery Backup)

The PSD supports a battery backup operation that

retains the contents of the SRAM in the event of a

power loss. The SRAM has a VSTBY pin (PC2) that

can be connected to an external battery. When

VCC becomes lower than VSTBY then the PSD will

automatically connect to VSTBY as a power source

to the SRAM. The SRAM Standby Current (ISTBY)

is typically 0.5µA. The SRAM data retention volt-

age is 2 V minimum. The battery-on indicator (VBA-

TON) can be routed to PC4. This signal indicates

when the VCC has dropped below the VSTBY volt-

age.

PSD Chip Select Input (CSI, PD2)

Pin PD2 of Port D can be configured in PSDsoft

Express as the CSI input. When low, the signal se-

lects and enables the internal Flash, EEPROM,

SRAM, and I/O for READ or WRITE operations in-

volving the PSD. A high on the CSI pin will disable

the Flash memory, EEPROM, and SRAM, and re-

duce the PSD power consumption. However, the

PLD and I/O pins remain operational when CSI is

High.

Note: There may be a timing penalty when using

the CSI pin depending on the speed grade of the

PSD that you are using. See the timing parameter

tSLQV in Table 63., page 95 or Table 64., page 95.

Input Clock

The PSD provides the option to turn off the CLKIN

input to the PLD to save AC power consumption.

The CLKIN is an input to the PLD AND array and

the Output Macrocells. During Power Down Mode,

or, if the CLKIN input is not being used as part of

the PLD logic equation, the clock should be dis-

abled to save AC power. The CLKIN will be dis-

connected from the PLD AND array or the

Macrocells by setting bits 4 or 5 to a ‘1’ in PMMR0.

Figure 34. Enable Power-down Flow Chart

Enable APD

Set PMMR0 Bit 1 = 1

PSD in Power

Down Mode

ALE/AS idle

for 15 CLKIN

clocks?

RESET

Yes

OPTIONAL

Disable desired inputs to PLD

by setting PMMR0 bits 4 and 5

and PMMR2 bits 2 through 6.

AI02892

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