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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PSD813F1 датащи(PDF) 61 Page - STMicroelectronics |
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PSD813F1 датащи(HTML) 61 Page - STMicroelectronics |
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61 / 110 page  61/110 PSD813F1 Port C – Functionality and Structure Port C can be configured to perform one or more of the following functions (see Figure 30): s MCU I/O Mode s CPLD Output – McellBC7-McellBC0 outputs can be connected to Port B or Port C. s CPLD Input – via the Input Macrocells (IMC) s Address In – Additional high address inputs using the Input Macrocells (IMC). s In-System Programming (ISP) – JTAG port can be enabled for programming/erase of the PSD device. (See the section entitled PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE, page 71, for more information on JTAG programming.) s Open Drain – Port C pins can be configured in Open Drain Mode s Battery Backup features – PC2 can be configured as a battery input pin (VSTBY). PC4 can be configured as a Battery-on Indica- tor output pin (VBATON), indicating when VCC is less than VBAT. Port C does not support Address Out mode, and therefore no Control Register is required. Pin PC7 may be configured as the DBE input in certain MCU interfaces. Figure 30. Port C Structure Note: 1. ISP or battery back-up. DATA OUT REG. DQ DQ WR WR MCELLBC[ 7:0] ENABLE PRODUCT TERM (.OE) READ MUX P D B CPLD - INPUT DIR REG. INPUT MACROCELL ENABLE OUT SPECIAL FUNCTION 1 SPECIAL FUNCTION 1 CONFIGURATION BIT DATA IN OUTPUT SELECT OUTPUT MUX PORT C PIN DATA OUT AI02888B |
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