DSP56857 datasheet(153/662 Pages) FREESCALE

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Introduction

On-Chip Clock Synthesis (OCCS), Rev. 4

Freescale Semiconductor

6-3

6.1 Introduction

The On-Chip Clock Synthesis (OCCS) module allows product design using an inexpensive

4MHz crystal or an external clock source to run the DSP56853/54/55/57/58 at any frequency

from 0 to 120MHz. The OCCS module is comprised of two major blocks: the Oscillator (OSC),

and the PLL/CGM (analog - Phase Locked Loop/digital - Clock Generation Module (CGM)).

The OSC output clocks feed the PLL/CGM block. The PLL/CGM generates a time clock for

Computer Operating Properly (COP) timer use. The PLL/CGM also generates a master clock

consumed by the System Integration Module (SIM). The SIM generates derivative clocks for

consumption by the core logic and IPBus peripherals.

The SIM divides the MSTR_CLK (typically 240MHz) by 2 to create the 56800E core clock

(typically 120MHz) and by 4 to create the IPBUS_CLK (typically 60 MHz). All peripherals on

the DSP56853/54/55/57/58 run off the IPBus clock frequency. The COP and TOD peripherals

also consumes the much lower frequency TIME_CLK (typically 31.25 KHz).

The PLL may be used to generate a high frequency clock from the low-frequency

crystal-referenced (or external clock driven) OSC circuit. The PLL provides an exact integer

multiple of the oscillator’s output reference frequency (Fref). The frequency multiplication is in

the range of 20 to 120.

The CGM controls the PLL’s output frequency. The CGM also selects between the PLL

(PLL_OUT) and OSC (Fref) as potential master clock sources and routes the selection to the

SIM. The CGM also contains circuitry to detect if the PLL is unlocked and generates an interrupt

signal for the condition.

Figure 6-1. OCCS Integration Overview

Out of reset, the CGMCR[SEL] control bit is 0, selecting the Fref path as the source of

MSTR_CLK. The core will proceed to execute code using a clock divided down from the

OSC

Oscillator

EXTAL

XTAL

PLL / CGM

Phase Locked Loop

Clock Generation Module

CGMCR[SEL]

(4 MHz)

(240 MHz)

BOLD represents default states or typical

conditions.

* see STOP Mode Features for further details

Time Of Day

COP

other peripherals

IPBB

IP Bus Bridge

SIM

System

Integration

Module

divide

by 4

56800E

Core

MSTR_CLK

(120 MHz)

(60 MHz)

TIME_CLK (31.25 KHz)

CLKOUT (30 MHz)

Loss_Of_Lock_Interrupt

OCCS

On-Chip Clock Synthesis

PLL_OUT

4 MHz

Ftime

(31.25 KHz)

Fref

(4 MHz)

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