AD9953ASV datasheet(34/42 Pages) AD

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PRELIMINARY TECHNICAL DATA

AD9953

Synchronization; Register Updates (I/O UPDATE)

Functionality of the SyncClk and I/O UPDATE

Data into the AD9953 is synchronous to the sync_clk signal (supplied externally to the user

on the SYNC_CLK pin). The I/O_UPDATE pin is sampled on the rising edge of the sync_clk.

Internally, sysclk is fed to a divide-by-4 frequency divider to produce the sync_clk signal.

The sync_clk signal is provided to the user on the SYNC_CLK pin. This enables synchronization

of external hardware with the device’s internal clocks. This is accomplished by forcing any

external hardware to obtain its timing from sync_clk. The I/O UPDATE signal coupled with

sync_clk is used to transfer internal buffer contents into the Control Registers of the device. The

combination of the sync_clk and I/O UPDATE pins provides the user with constant latency relative

to sysclk and also ensures phase continuity of the analog output signal when a new tuning word or

phase offset value is asserted. Figure E demonstrates an I/O Update timing cycle and

synchronization.

Notes to synchronization logic:

1) The I/O UPDATE signal is edge detected to generate a single rising edge clock signal

that drives the register bank flops. The I/O UPDATE signal has no constraints on duty

cycle. The minimum low time on I/O UPDATE is one sync_clk clock cycle.

2) The I/O UPDATE pin is setup and held around the rising edge of sync_clk and has zero

hold time and 10ns setup time.

REV. PrB 1/30/03

Page 34

Analog Devices, Inc.

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