AD9953ASV datasheet(8/42 Pages) AD

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PRELIMINARY TECHNICAL DATA

AD9953

Hardware Pin Descriptions

Pin #

Pin Name

I/O

Description

I/O UPDATE

The rising edge transfers the contents of the internal

buffer memory to the IO Registers.

2,34

DVDD

Digital power supply pins.

3,33,

DGND

Digital power ground pins.

4,6,

13,16,

18,19,

25,27,

AVDD

Analog power supply pins.

5,7,

14,15,

17,22,

26,

30,31

AGND

Analog power ground pins.

OSCB/REFCLKB

Complementary reference clock/oscillator input

(400MHz max.). NOTE: When the REFCLK port is

operated in single-ended mode, then REFCLKB should

be decoupled to AVDD with a 0.1

µF capacitor.

OSC/REFCLK

Reference clock/oscillator input (400 MHz max.). See

Clock Input section of datasheet for details on the

REFCLK/OSCILLATOR operation.

Crystal Out

Output of the oscillator section.

ClkModeSelect

Control pin for the oscillator section. When high, the

oscillator section is enabled. When low, the oscillator

section is bypassed.

LOOP_FILTER

This Pin provides the connection for the external zero

compensation network of the REFCLK Multiplier’s PLL

loop filter. The network consists of a 1K ohm resistor in

series with a 0.1

µF capacitor tied to AVDD.

IOUTB

Complementary DAC output.

IOUT

DAC output.

DACBP

DAC “biasline” decoupling pin.

DAC_Rset

A resistor (3.85K

Ω nominal) connected from AGND to

DAC_Rset establishes the reference current for the

DAC.

No connect.

PwrDwnCtl

Input pin used as an external power down control. See

the External Power Down Control section of this

document for details.

REV. PrB 1/30/03

Page 8

Analog Devices, Inc.

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