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PRELIMINARY TECHNICAL DATA

AD9953

Bi-directional Ramp mode allows the AD9953 to offer a symmetrical sweep between two

frequencies using the Profile<0> signal as the control input. The AD9953 is programmed for Bi-

directional Ramp mode by writing the RAM Enable bit true and the RAM Mode Control bits of

RSCW0 to logic 010(b). In Bi-directional Ramp mode, the Profile<1> input is ignored and the

Profile<0> input is the ramp direction indicator. In this mode, the memory is not segmented and

uses only a single beginning and final address. The address registers that affect the control of the

RAM are located in the RSCW associated with profile 0.

Upon entering this mode (via an I/O UPDATE or changing Profile<0>), the RAM address

generator loads the RAM Segment Beginning Address bits of RSCW0 and the Ramp Rate Timer

loads the RAM Segment Address Ramp Rate bits. The RAM drives data from the beginning

address and the ramp rate timer begins to count down to 1. While operating in this mode, toggling

the Profile<0> pin does not cause the device to generate an internal I/O UPDATE. That is to say,

when the Profile<0> pin is acting as the ramp direction indicator, any transfer of data from the I/O

buffers to the internal registers can only be initiated by a rising edge on the I/O UPDATE pin.

RAM address control now is a function of the Profile<0> input. When the Profile<0> bit is a logic

one, the RAM address generator increments to the next address when the ramp rate timer

completes a cycle (and reloads to start the timer again). As in the Ramp-Up mode, this sequence

continues until the RAM address generator has incremented to an address equal to the final address

as long as the Profile<0> input remains high. If the Profile<0> input goes low, the RAM address

generator immediately decrements and the ramp rate timer is reloaded. The RAM address

generator will continue to decrement at the ramp rate period until the RAM address is equal to the

beginning address as long as the Profile<0> input remains low.

The sequence of ramping up and down is controlled via the Profile<0> input signal for as long as

the part is programmed into this mode. The no dwell bit is a “don’t care” in this mode as is all data

in the RAM Segment Control Words associated with profiles 1,2,3. Only the information in the

RAM Segment Control Word for profile 0 is used to control the RAM in the Bi-Directional Ramp

Mode.

Notes to the Bi-directional Ramp mode:

1) The user must insure that the beginning address is lower than the final address.

2) Issuing an I/O UPDATE automatically terminates the current sweep causing the starting

address to be reloaded and the ramp rate timer to initialize.

3) Setting the RAM destination bit true such that the RAM output drives the phase-offset adder

is valid. While the above discussion describes a frequency sweep, a phase sweep operation

is also available.

Continuous Bi-directional Ramp Mode

REV. PrB 1/30/03

Page 26

Analog Devices, Inc.

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