AD9953ASV datasheet(18/42 Pages) AD

номер детали	AD9953ASV

подробное описание детали	400 MSPS 14-Bit, 1.8V CMOS Direct Digital Synthesizer

PDF	42 Pages

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производитель	AD [Analog Devices]

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18 / 42 page

PRELIMINARY TECHNICAL DATA

AD9953

CFR1<20>: Amplitude dither enable bit.

When CFR1<20> = 0 (default), amplitude dithering is disabled.

When CFR1<20> = 1, amplitude dithering is enabled.

CFR1<19>: Phase bit <16> dither enable bit.

When CFR1<19> = 0 (default), phase dithering for truncated phase words, bit 16 of

<31:13>, is disabled.

When CFR1<19> = 1, phase dithering for truncated phase words, bit 16 of <31:13>,

is enabled.

CFR1<18>: Phase bit <15> dither enable bit.

When CFR1<18> = 0 (default), phase dithering for truncated phase words, bit 15 of

<31:13>, is disabled.

When CFR1<18> = 1, phase dithering for truncated phase words, bit 15 of <31:13>,

is enabled.

CFR1<17>: Phase bit <14> dither enable bit.

When CFR1<17> = 0 (default), phase dithering for truncated phase words, bit 14 of

<31:13>, is disabled.

When CFR1<17> = 1, phase dithering for truncated phase words, bit 14 of <31:13>,

is enabled.

CFR1<16>: Phase bit <13> dither enable bit.

When CFR1<16> = 0 (default), phase dithering for truncated phase words, bit 13 of

<31:13>, is disabled.

When CFR1<16> = 1, phase dithering for truncated phase words, bit 13 of <31:13>,

is enabled.

CFR1<14>: Auto Clear Frequency Accumulator bit.

When CFR1<14> = 0 (default), a new delta frequency word is applied to the input, as

in normal operation, but not loaded into the accumulator.

REV. PrB 1/30/03

Page 18

Analog Devices, Inc.

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