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PRELIMINARY TECHNICAL DATA

AD9953

When CFR1<9> = 1, the serial data I/O pin (SDIO) is configured as an input only pin

(3-wire serial programming mode).

CFR1<8>: LSB First.

When CFR1<8> = 0 (default), MSB first format is active.

When CFR1<8> = 1, the serial interface accepts serial data in LSB first format.

CFR1<7>: Digital Power Down bit.

When CFR1<7> = 0 (default), all digital functions and clocks are active.

When CFR1<7> = 1, all non-IO digital functionality is suspended and all heavily

loaded clocks are stopped. This bit is intended to lower the digital power to nearly

zero, without shutting down the PLL clock multiplier function or the DAC.

CFR1<5>: DAC Power Down bit.

When CFR1<5> = 0 (default), the DAC is enabled for operation.

When CFR1<5> = 1, the DAC is disabled and is in its lowest power dissipation state.

CFR1<4>: Clock Input Power Down bit.

When CFR1<4> = 0 (default), the clock input circuitry is enabled for operation.

When CFR1<4> = 1, the clock input circuitry is disabled and the device is in its

lowest power dissipation state.

CFR1<3>: External Power Down Mode.

When CFR1<3> = 0 (default) the external power down mode selected is the “fast

recovery power down” mode. In this mode, when the PwrDwnCtl input pin is high,

the digital logic and the DAC digital logic are powered down. The DAC bias

circuitry, comparator, PLL, oscillator, and clock input circuitry is NOT powered

down.

When CFR1<3> = 1, the external power down mode selected is the “full power

down” mode. In this mode, when the PwrDwnCtl input pin is high, all functions are

powered down. This includes the DAC and PLL, which take a significant amount of

time to power up.

REV. PrB 1/30/03

Page 20

Analog Devices, Inc.

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