AD9953ASV datasheet(40/42 Pages) AD

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PRELIMINARY TECHNICAL DATA

AD9953

operation is complete. All data written to (read from) the AD9953 must be (will be) in MSB first

order. If the LSB mode is active, the serial port controller will generate the least significant byte

address first followed by the next greater significant byte addresses until the IO operation is

complete. All data written to (read from) the AD9953 must be (will be) in LSB first order.

Example Operation

To write the Amplitude Scale Factor register in MSB first format apply an instruction byte of 02h

(serial address is 00010(b)). From this instruction, the internal controller will generate an internal

byte address of 07h (see the register map) for the first data byte written and an internal address of

08h for the next byte written. Since the Amplitude Scale Factor register is two bytes wide, this

ends the communication cycle.

To write the Amplitude Scale Factor register in LSB first format apply an instruction byte of 40h.

From this instruction, the internal controller will generate an internal byte address of 07h (see the

Since the Amplitude Scale Factor register is two bytes wide, this ends the communication cycle.

RAM I/O Via Serial Port

Accessing the RAM via the serial port is identical to any other serial IO operation except that the

number of bytes transferred is determined by the address space between the beginning address and

the final address as specified in the current RAM Segment Control Word (RSCW). The final

address describes the most significant word address for all IO transfers and the beginning address

specifies the least significant address.

RAM I/O supports MSB/LSB first operation. When in MSB first mode, the first data byte will be

for the most significant byte of the memory address described by the final address with the

remaining three bytes making up the lesser significant bytes of that address. The remaining bytes

come in most significant to least significant, destined for RAM addresses generated in descending

order until the final four bytes are written into the address specified as the beginning address.

When in LSB first mode, the first data byte will be for the least significant byte of the memory

(specified by the beginning address) with the remaining three bytes making up the greater

significant bytes of that address. The remaining bytes come in least significant to most significant,

destined for RAM addresses generated in ascending order until the final four bytes are written into

the memory address described by the final address. Of course, the bit order for all bytes is least

significant to most significant first when in the LSB first bit is set. When the LSB first bit is

cleared (default) the bit order for all bytes is most significant to least significant.

The RAM uses serial address 01011(b), so the instruction byte to write the RAM is 0Bh, in MSB

first notation. As mentioned above, the RAM addresses generated are specified by the beginning

and final address of the RSCW currently selected by the Profile<1:0> pins.

REV. PrB 1/30/03

Page 40

Analog Devices, Inc.

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