PRELIMINARY TECHNICAL DATA

AD9953

CFR1<1>: SyncClk Disable bit.

When CFR1<1> = 0 (default), the SyncClk pin is active.

When CFR1<1> = 1, the SyncClk pin assumes a static logic 0 state (disabled). In

this state the pin drive logic is shut down to keep noise generated by the digital

circuitry at a minimum. However, the synchronization circuitry remains active

(internally) to maintain normal device timing.

CFR1<0>: Not used. Leave at 0.

NOTE: Assertion of this bit may cause the SyncClk pin to momentarily stop generating a Sync Clock signal. The device will not be operational during the

re-synchronization period.

Control Function Register #2 (CFR2)

The CFR2 is comprised of three bytes located in parallel addresses 06h-04h. The CFR2 is used to

control the various functions, features, and modes of the AD9953, primarily related to the analog

sections of the chip. All bits of the CFR2 will be routed directly to the Analog section of the

AD9953 as a single 24-bit bus labeled CFR2<23:0>.

CFR2<11>: High Speed Sync Enable bit.

When CFR2<11> = 0 (default) the High Speed Sync enhancement is off.

When CFR2<11> = 1, the High Speed Sync enhancement is on. See the

Synchronizing Multiple AD9953s section of this document for details.

CFR2<10>: Hardware Manual Sync Enable bit.

When CFR2<10> = 0 (default) the Hardware Manual Sync function is off.

When CFR2<11> = 1, the Hardware Manual Sync function is enabled. While this bit

is set, a rising edge on the SYNC_IN pin will cause the device to advance the

SYNC_CLK rising edge by one REFCLK cycle. Unlike the software manual sync

bit, this bit does not self-clear. Once the hardware manual sync mode is enabled, it

will stay enabled until this bit is cleared. See the Synchronizing Multiple AD9953s

section of this document for details.

REV. PrB 1/30/03

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Analog Devices, Inc.