AD9953ASV datasheet(42/42 Pages) AD

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PRELIMINARY TECHNICAL DATA

AD9953

REV. PrB 1/30/03

Page 42

Analog Devices, Inc.

When the CFR1<3> bit is zero, and the PwrDwnCtl input pin is high, the AD9953 is put into a

“fast recovery power down” mode. In this mode, the digital logic and the DAC digital logic are

powered down. The DAC bias circuitry, comparator, PLL, oscillator, and clock input circuitry is

NOT powered down. The comparator can be powered down by setting the Comparator Power

Down Bit, CFR1<6> =1.

When the CFR1<3> bit is high, and the PwrDwnCtl input pin is high, the AD9953 is put into the

“full power down” mode. In this mode, all functions are powered down. This includes the DAC

and PLL, which take a significant amount of time to power up.

When the PwrDwnCtl input pin is high, the individual power down bits (CFR1<7>, <5:4>) are

invalid (don’t care) and are unused; however the Comparator Power Down bit, CFR1<6>, will

continue to control the power-down of the comparator. When the PwrDwnCtl input pin is low, the

individual power down bits control the power down modes of operation.

NOTE – The power down signals are all designed such that a logic 1 indicates the low power mode

and a logic zero indicates the active, or powered up mode.

The table below indicates the logic level for each power down bit that drives out of the AD9953

core logic to the analog section and the digital clock generation section of the chip for the External

Power Down operation.

Control

Mode active

Description

PwrDwnCtl = 0

CFR1<3> don’t

care

Software

Control

Digital power down = CFR1<7>

Comparator power down = CFR1<6>

DAC power down = CFR1<5>

Input Clock power down = CFR1<4>

PwrDwnCtl = 1

CFR1<3> = 0

External

Control,

Fast recovery

power down

mode

Digital power down = 1’b1;

Comparator power down = 1’b0 OR CFR1<6>;

DAC power down = 1’b0;

Input Clock power down = 1’b0;

PwrDwnCtl = 1

CFR1<3> = 1

External

Control,

Full power down

mode

Digital power down = 1’b1;

Comparator power down = 1’b1;

DAC power down = 1’b1;

Input Clock power down = 1’b1;

Table 7 Power Down Control Functions

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