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PRELIMINARY TECHNICAL DATA

AD9953

Frequency Tuning Word 0 (FTW0)

The Frequency Tuning Word is a 32-bit register that controls the rate of accumulation in the phase

accumulator of the DDS core. Its specific role is dependent on the device mode of operation.

Phase Offset Word (POW)

The Phase Offset Word is a 14-bit register that stores a phase offset value. This offset value is

added to the output of the phase accumulator to offset the current phase of the output signal. The

exact value of phase offset is given by the following formula:













360

214

POW

When the RAM enable bit is set, CFR1<31> = 1, and the RAM destination is cleared,

CFR1<30>=0, the RAM supplies the phase offset word and this register has no affect on device

operation.

Frequency Tuning Word 1 (FTW1)

The Frequency Tuning Word is a 32-bit register that controls the rate of accumulation in the phase

accumulator of the DDS core. Its specific role is dependent on the device mode of operation.

RAM Segment Control Words 0,1,2,3 (RSCW0) (RSCW1) (RSCW2), (RSCW3)

Registers h’07, h’08, h’09 and h’0A act as the RAM segment Control words, RSCW0, RSCW1,

RCSW2 and RCSW3 respectively. Each of the RAM Segment Control Words contains a 3-bit

Mode Control value, a ‘No Dwell’ bit, a 10-bit Beginning Address, a 10-bit Final Address and a

16-bit Address Ramp Rate. Please see the section on RAM modes of operation for details on how

each of these values works in the various RAM modes of operation.

RAM

The AD9953 incorporates a 1024x32 block of SRAM. The RAM is bi-directional single-

port. That is to say, both READ and WRITE operations from and to the RAM are valid, but they

cannot occur simultaneously. WRITE operations from the serial I/O port have precedence, and if

an attempt to WRITE to RAM is made during a READ operation, the READ operation will be

halted. The RAM is controlled in multiple ways, dictated by modes of operation described in the

RAM Segment Control Word <7:5> as well as data in the Control Function Register. Read/write

control for the RAM will be described for each mode supported.

When the RAM Enable bit (CFR1<31>) is set, the RAM output optionally drives the input to the

phase accumulator OR the phase offset adder, depending upon the state of the “RAM Destination”

bit (CFR1<30>). If CFR1<30> is a logic one, the RAM output is connected to the Phase Offset

adder and supplies the phase offset control word(s) for the device. When CFR1<30> is logic zero

(default condition), the RAM output is connected to the input of the phase accumulator and

supplies the frequency tuning word(s) for the device. When the RAM output drives the phase

accumulator, the Phase Offset Word (POW, hex address 05h) drives the phase-offset adder.

REV. PrB 1/30/03

Page 23

Analog Devices, Inc.

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