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PRELIMINARY TECHNICAL DATA

AD9953

Notes on Serial Port Operation

1) The AD9953 serial port configuration bits reside in bits 8 and 9 of CFR1 (address 00h). The

configuration changes immediately upon writing to this register. For multi-byte transfers,

writing to this register may occur during the middle of a communication cycle. Care must be

taken to compensate for this new configuration for the remainder of the current

communication cycle.

2) The system must maintain synchronization with the AD9953 or the internal control logic

will not be able to recognize further instructions. For example, if the system sends an

instruction byte that describes writing a 2-byte register, then pulses the SCLK pin for a 3-

byte write (24 additional SCLK rising edges), communication synchronization is lost. In this

case, the first 16 SCLK rising edges after the instruction cycle will properly write the first

two data bytes into the AD9953, but the next eight rising SCLK edges are interpreted as the

next instruction byte, not the final byte of the previous communication cycle. In the case

where synchronization is lost between the system and the AD9953, the SYNC I/O pin

provides a means to re-establish synchronization without re-initializing the entire chip. The

SYNC I/O pin enables the user to reset the AD9953 state machine to accept the next eight

SCLK rising edges to be coincident with the instruction phase of a new communication

cycle. By applying and removing a “high” signal to the SYNC I/O pin, the AD9953 is set to

once again begin performing the communication cycle in synchronization with the system.

Any information that had been written to the AD9953 registers during a valid

communication cycle prior to loss of synchronization will remain intact.

3) Reading profile registers requires that the profile select pins (Profile<1:0>) be configured to

select the desired register bank. When reading a register that resides in one of the profiles,

the register address acts as an offset to select one of the registers among the group of

registers defined by the profile. While the profile select pins select the appropriate register

group.

Power Down Functions of the AD9953

The AD9953 supports an externally controlled, or hardware, power down feature as well as the

more common software programmable power down bits found in previous ADI DDS products.

The software control power down allows the DAC, Comparator, PLL, Input Clock circuitry and

the digital logic to be individually power down via unique control bits (CFR1<7:4>). With the

exception of CFR1<6>, these bits are not active when the externally controlled power down pin

(PwrDwnCtl) is high. External Power Down Control is supported on the AD9953 via the

PwrDwnCtl input pin. When the PwrDwnCtl input pin is high, the AD9953 will enter a power

down mode based on the CFR1<3> bit. When the PwrDwnCtl input pin is low, the external power

down control is inactive.

REV. PrB 1/30/03

Page 41

Analog Devices, Inc.

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