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PRELIMINARY TECHNICAL DATA

AD9953

The CrystalOut pin is static until the CFR2<1> bit is set, enabling the output. The drive strength of

the CrystalOut pin is typically very low, so this signal should be buffered prior to using it to drive

any loads.

Serial Port Operation

With the AD9953, the Instruction Byte specifies read/write operation and register address. Serial

operations on the AD9953 occur only at the register level, not the byte level. For the AD9953, the

serial port controller recognizes the Instruction Byte register address and automatically generates

the proper register byte address. In addition, the controller expects that all bytes of that register will

be accessed. It is a requirement that all bytes of a register be accessed during serial I/O

operations, with one exception. The SYNCIO function can be used to abort an IO operation

thereby allowing less than all bytes to be accessed.

There are two phases to a communication cycle with the AD9953. Phase 1 is the instruction cycle,

which is the writing of an instruction byte into the AD9953, coincident with the first eight SCLK

rising edges. The instruction byte provides the AD9953 serial port controller with information

regarding the data transfer cycle, which is Phase 2 of the communication cycle. The Phase 1

instruction byte defines whether the upcoming data transfer is read or write and the serial address

of the register being accessed. [Note – the serial address of the register being accessed is NOT the

same address as the bytes to be written. See the Example Operation section below for details].

The first eight SCLK rising edges of each communication cycle are used to write the instruction

byte into the AD9953. The remaining SCLK edges are for Phase 2 of the communication cycle.

Phase 2 is the actual data transfer between the AD9953 and the system controller. The number of

bytes transferred during Phase 2 of the communication cycle is a function of the register being

accessed. For example, when accessing the Control Function Register 2, which is three bytes wide,

Phase 2 requires that three bytes be transferred. If accessing the Frequency Tuning Word, which is

four bytes wide, Phase 2 requires that four bytes be transferred. After transferring all data bytes per

the instruction, the communication cycle is completed.

At the completion of any communication cycle, the AD9953 serial port controller expects the next

8 rising SCLK edges to be the instruction byte of the next communication cycle.All data input to

the AD9953 is registered on the rising edge of SCLK. All data is driven out of the AD9953 on the

falling edge of SCLK. Figures 34 - 37 are useful in understanding the general operation of the

AD9953 Serial Port.

REV. PrB 1/30/03

Page 37

Analog Devices, Inc.

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