WM8912 datasheet(101/129 Pages) CIRRUS

101 / 129 page

Production Data

WM8912

PD, Rev 4.1, February 2013

101

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

1001 to 1111 = Reserved

4:0

BCLK_DIV

[4:0]

0_0100

BCLK Frequency (Master Mode)

00000 = SYSCLK

00001 = SYSCLK / 1.5

00010 = SYSCLK / 2

00011 = SYSCLK / 3

00100 = SYSCLK / 4

00101 = SYSCLK / 5

00110 = SYSCLK / 5.5

00111 = SYSCLK / 6

01000 = SYSCLK / 8 (default)

01001 = SYSCLK / 10

01010 = SYSCLK / 11

01011 = SYSCLK / 12

01100 = SYSCLK / 16

01101 = SYSCLK / 20

01110 = SYSCLK / 22

01111 = SYSCLK / 24

10000 = SYSCLK / 25

10001 = SYSCLK / 30

10010 = SYSCLK / 32

10011 = SYSCLK / 44

10100 = SYSCLK / 48

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

R27 (1Bh)

Audio

Interface 3

LRCLK_DIR

Audio Interface LRC Direction

0 = LRC is input

1 = LRC is output

10:0

LRCLK_RATE

[10:0]

000_0100_

0000

LRC Rate (Master Mode)

LRC clock output = BCLK / LRCLK_RATE

Integer (LSB = 1)

Valid range: 8 to 2047

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

R30 (1Eh)

DAC Digital

Volume Left

DAC_VU

DAC Volume Update

Writing a 1 to this bit causes left and right DAC volume

to be updated simultaneously

7:0

DACL_VOL

[7:0]

1100_0000 Left DAC Digital Volume

00h = Mute

01h = -71.625dB

02h = -71.250dB

… (0.375dB steps)

C0h to FFh = 0dB

WM8912 датащи(PDF) 101 Page - Cirrus Logic

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