PC97338VLJ datasheet(120/221 Pages) NSC

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3.6.24 The WRITE DATA Command

The WRITE DATA command receives data from the

host and writes logical sectors containing a normal

data Address Mark (AM) to the selected drive.

This command is like the READ DATA command, ex-

cept that the data is transferred from the microproces-

sor to the controller instead of the other way around.

Command Phase

See the READ DATA command starting on page 105

for a description of these bytes.

The controller waits the Delay Before Processing time

before starting execution.

If implied seeks are enabled, i.e., IPS in the second

command phase byte is 1, the operations performed

by SEEK and SENSE INTERRUPT commands are

performed (without these commands being issued).

Execution Phase

Data is transferred from the system to the controller

via DMA or non-DMA modes and written to the

disk.See “Execution Phase” starting on page 85 for a

description of these data transfer modes.

The controller starts the data separator and waits for

it to find the address field of the next sector. The con-

troller compares the address ID (track number, head

number, sector number, bytes-per-sector code) with

the ID specified in the command phase.

If there is no match, the controller waits to find the

next sector address field. This process continues until

the desired sector is found. If an error condition oc-

curs, the Interrupt Control (IC) bits (bits 7,6) in ST0

are set to abnormal termination, and the controller en-

ters the result phase. See “Bits 7,6 - Interrupt Code

(IC)” on page 89

Possible errors are:

• The microprocessor aborted the command by writ-

ing to the FIFO.

If there is no disk in the drive, the controller gets

stuck. The microprocessor must then write a byte

to the FIFO to advance the controller to the result

phase.

• Two pulses of the INDEX signal were detected

since the search began, and no valid ID was

found.

If the track address differs, either the Wrong Track

bit (bit 4) or the Bad Track bit (bit 1) (if the track ad-

dress is FF hex) is set in result phase Status reg-

ister 2 (ST2). See Section 3.5.3 on page 90.

If the head number, sector number or bytes-per-

sector code did not match, the Missing Data bit (bit

2) is set in result phase Status register 1 (ST1).

If the Address Mark (AM) is not found, the Missing

Address Mark bit (bit 0) is set in ST1.

Section 3.5.2 on page 89 describes the bits of

ST1.

• A CRC error was detected in the address field. In

this case the CRC Error bit (bit 5) is set in ST1.

• The controller detected an active the Write Protect

(WP) disk interface input signal, and set bit 1 of

ST1 to 1.

If the correct address field is found, the controller

waits for all (conventional drive mode) or part (per-

pendicular drive mode) of gap 2 to pass. See Figure

58 on page 99. The controller then writes the pream-

ble field, Address Marks (AM) and data bytes to the

data field. The microprocessor transfers the data

bytes to the controller.

After writing the sector, the controller reads the next

logical sector, unless one or more of the following ter-

mination conditions occurs:

• The DMA controller asserted the Terminal Count

(TC) signal to indicate that the operation terminat-

ed. The Interrupt Code (IC) bits (bits 7,6) in ST0

are set to normal termination (00). See page 89.

• The last sector address (of side 1, if the Multi-

Track enable bit (MT) was set to 1) was equal to

the End of Track sector number. The End of Track

bit (bit 7) in ST1 is set. The IC bits in ST0 are set

to abnormal termination (01). This is the expected

condition during non-DMA transfers.

• Overrun error. The Overrun bit (bit 4) in ST1 is set.

The Interrupt Code (IC) bits (bits 7,6) in ST0 are

set to abnormal termination (01). If the micropro-

cessor cannot service a transfer request in time,

the last correctly written byte is written to the disk.

If the Multi-Track (MT) bit was set in the opcode com-

mand byte, and the last sector of side 0 has been

transferred, the controller continues with side 1.

7654

3210

MFM

0101

IPS

DS1

DS0

Track Number

Head Number

Sector Number

Bytes-Per-Sector Code

End of Track (EOT) Sector Number

Bytes Between Sectors - Gap 3

Data Length (Obsolete)

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