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PC97338VLJ датащи(PDF) 117 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
номер детали PC97338VLJ
подробное описание детали  ACPI 1.0 and PC98/99 Compliant SuperI/O
PDF  221 Pages
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производитель  NSC [National Semiconductor (TI)]
домашняя страница  http://www.national.com
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PC97338VLJ датащи(HTML) 117 Page - National Semiconductor (TI)

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TABLE 58. Constant Multipliers for Delay After Processing Factor and Delay Ranges
TABLE 59. Constant Multipliers for Delay Before Processing Factor and Delay Ranges
Data Transfer
Rate (bps)
Bit 7 of MODE (TMR) = 0
Bit 7 of MODE (TMR) = 1
Constant Multiplier Permitted Range (msec) Constant Multiplier Permitted Range (msec)
1 M
8
8 -128
512
512 - 8192
500 K
16
16 - 256
512
512 - 8192
300 K
80 / 3
26.7 - 427
2560 / 3
853 - 13653
250 K
32
32 - 512
1024
1024 -16384
Data Transfer
Rate (bps)
Bit 7 of MODE (TMR) = 0
Bit 7 of MODE (TMR) = 1
Constant Multiplier Permitted Range (msec) Constant Multiplier
Permitted Range
(msec)
1 M
1
1 -128
32
32 - 4096
500 K
1
1 -128
32
32 - 4096
300 K
10 / 3
3.3 - 427
160 / 3
53 - 6827
250 K
4
4 - 512
64
64 - 8192
Bits 7-4 - STEP Time Interval Value (SRT)
These bits specify a value that is used to calculate
the time interval between successive STEP signal
pulses during a SEEK, IMPLIED SEEK, RECALI-
BRATE, or RELATIVE SEEK command.
Table 60 shows how this value is used to calculate
the actual time interval.
TABLE 60. STEP Time Interval Calculation
Third Command Phase Byte
Bit 0 - DMA
This bit selects the data transfer mode in the exe-
cution phase of a read, write, or scan operation.
Data can be transferred between the microproces-
sor and the controller during execution in DMA
mode or in non-DMA mode, i.e., interrupt transfer
mode or software polling mode.
See “Execution Phase” on page 85 for a descrip-
tion of these modes.
0 - DMA mode is selected.
1 - Non-DMA mode is selected.
Bits 3-0 - Delay Before Processing Factor
These bits specify a factor that is multiplied by a
constant to determine the delay before command
processing starts, i.e., from selection of a drive
motor until a read or write operation starts.
The value of the Motor Timer Values (TMR) bit (bit
7) of the second command phase byte in the
MODE command determines which group of con-
stants and delay ranges to use. See “Bit 7 - Motor
Timer Values (TMR)” on page 101.
The specific constant that will be multiplied by this
factor to determine the actual delay before pro-
cessing for each data transfer rate is shown in Ta-
ble 59.
Use the smallest possible value for this factor, ex-
cept 0, i.e., 1. If this factor is 0, the value128 is
used.
Execution Phase
Internal registers are written.
Result Phase
None.
Data Transfer
Rate (bps)
Calculation of
Time Interval
Permitted
Range (msec)
1 M
(16
− SRT) / 2
0.5 - 8
500 K
(16
− SRT)
1 - 16
300 K
(16
− SRT) x 1.67
1.67 - 26.7
250 K
(16
− SRT) x 2
2 - 32



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