PC97307 datasheet(215/218 Pages) NSC

215 / 218 page

215

Glossary

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MCR

Modem Control Register for UART1 (logical device

6, offset 04h) and for UART2 (logical device 5,

bank 0, offset 04h).

MSB

Most Signiﬁcant Byte or Bit.

MSR

Main Status Register of the Floppy Disk Controller

(FDC) (logical device 3, offset 4h) and Modem Sta-

tus Register for UART1 for read operations (logical

device 6, offset 06h) and for UART2 (logical device

5, bank 0, offset 06h).

Non-Extended UART Operation Modes

These UART operation modes support only UART

operations that are standard for 15450 or 16550A

devices.

NVM

Non-volatile memory.

P_BGDH and P_BGDL

Pipeline Baud rate Generator Divisor buffer (High

and Low bytes) for UARTs. (Logical devices 5 and

6, bank 5, offsets 01h and 00h, respectively.)

PIO

Programmable Input/Output.

P_MDR

Pipeline Mode Register for UARTs. (Logical devic-

es 5 and 6, bank 5, offset 02h.)

Plug and Play

A design philosophy and a set of speciﬁcations that

describe hardware and software changes to the PC

and its peripherals that automatically identify and

arbitrate resource requirements among all devices

and buses on the system. Plug and Play is some-

times abbreviated as PnP.

Power Management.

PMC1, PMC2 and PMC3

Power Management Control registers of logical de-

vice 8 at offsets 02h, 03h and 04h, respectively.

PnP

Sometimes used to indicate Plug and Play.

PnP Mode

In this mode, the interrupts, the DMA channels and

the base address of the FDC, UARTs, KBC, RTC,

GPIO, APC and the Parallel Port of the part are ful-

ly Plug and Play.

PP Confg0

Internal conﬁguration register of the Parallel Port in

Extended Capabilities Port (ECP) modes. (Logical

device 4, second level offset 05h.)

Precompensation

Also called write precompensation, is a way of pre-

conditioning the

WDATA output signal to adjust for

the effects of bit shift on the data as it is written to

the disk surface.

RBR

Receiver Buffer Register for UART1, read opera-

tions only (logical device 6, offset 00h, divisor latch

registers not accessible, bit 7 of LCR = 0).

RCCFG

Consumer Remote Control Conﬁguration register

for UART2. (Logical device 5, bank 7, offset 02h.)

RLC

Run Length Count byte for parallel ports.

RLE

Run Length Expander for parallel ports.

RLR

RAM Lock Register for Advanced Power Control

(APC). (Logical device 2, offset 47h.)

RSR

Internal Receiver Shift Register for UART1.

RTC

Real-Time Clock.

RXDR

Receiver Data Register for read cycles for UART2.

(Logical device 5, bank 0, offset 00h.)

RXFLV

Reception FIFO Level for UART2. (Logical device

5, bank 2, offset 07h.)

SCR

Scratch Register for UART1 (logical device 6, off-

set 07h) and for UART2 in UART operation mode

(logical device 5, bank 0, offset 07h).

SH_FCR

Shadow of the FIFO Control Register (FCR) for

UART2 for read operations. (Logical device 5, bank

3, offset 02h.)

SH_LCR

Shadow of the Line Control Register (LCR) for

UART2 for read operations. (Logical device 5, bank

3, offset 01h.)

Sharp IR

Sharp Infrared.

Sharp IR Mode

In this mode, the part supports a Sharp Infrared in-

terface.

SIO

SuperI/O, sometimes used to refer to a chip that

has

SuperI/O

capabilities,

e.g.,

the

PC87307/PC97307 VUL device.

SIR

Serial Infrared.

SIR_PW

SIR Pulse Width control for UART2. (Logical device

5, bank 6, offset 02h.)

SPP

The Standard Parallel Port conﬁguration of the Par-

allel Port device (Logical device 4) supports the

Compatible SPP mode and the Extended PP

mode.

SRA and SRB

Status Registers A and B of the Floppy Disk Con-

troller (FDC). (Logical device 3, offsets 0h and 1h,

respectively.)

ST0, ST1, ST2 and ST3

Status registers 0, 1, 2 and 3 of the Floppy Disk

Controller (FDC).

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