PC97307 datasheet(214/218 Pages) NSC

214 / 218 page

214

Glossary

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DSR

Data rate Select Register of the Floppy Disk Con-

troller (FDC) for write operations (logical device 3,

offset 4h) and the Data Status Register in Extend-

ed Capabilities Port (ECP) modes (logical device 4,

offset 001h).

DTR

Data Register of the parallel port in SPP or EPP

modes. (Logical device 4, offset 00h.)

EAR

Extended Auxiliary Register of the parallel port in

Extended Capabilities Port (ECP) modes. (Logical

device 4, offset 405h.)

ECP

Extended Capabilities Port.

ECR

Extended Control Register for the parallel port in

Extended Capabilities Port (ECP) modes. (Logical

device 4, offset 402h.)

EDR

Extended Data Register for the parallel port in ex-

tended Capabilities Port (ECP) modes. (Logical de-

vice 4, offset 404h.).

EIR

Extended Index Register of the parallel port Ex-

tended Capabilities Port (ECP) modes (logical de-

vice 4, offset 403h) and Event Identiﬁcation

visor latch registers not accessible, bit 7 of LCR =

0) and for UART2 for read cycles (logical device 5,

bank 0, offset 02h).

Extended UART Operation Mode

This UART operation mode supports standard

16450 and 16550A UART operations plus addition-

al interrupts and DMA features. It does not include

infrared or Consumer Remote Control modes.

EPP

Enhanced Parallel Port.

EXCR1 and EXCR2

Extended Control Registers 1 and 2 for UART2.

(Logical device 5, bank 2, offsets 02h and 04h, re-

spectively.)

FCR

The FIFO Control Register for UART1 (logical de-

vice 6, offset 02h) and for UART2 for write cycles

(logical device 5, bank 0, offset 02h).

FDC

Floppy Disk Controller.

FDD

Floppy Disk Drive.

FER1 and FER2

Function Enable Registers of the Power Manage-

ment device (Logical device 8, offsets 00h and 01h,

respectively.).

FIFO

Data register (FIFO queue) of the Floppy Disk Con-

troller (FDC). (Logical device 3, offset 05h.)

GPIO

General Purpose I/O - I/O pins available for general

use.

IER

The Interrupt Enable Register for UART1 (logical

device 6, offset 01h, divisor latch registers not ac-

cessible, bit 7 of LCR = 0) and for UART2 (logical

device 5, bank 0, offset 01h).

IIR

The Interrupt Identiﬁcation Register for UART1.

(Logical device 6, offset 02h.)

Index

The Index register is a pointer that is used to ad-

dress other registers.

InfraRed.

IRCFG1, IRCFG3 and IRCFG4

Infrared module Conﬁguration registers for UART2.

(Logical device 5, bank 7, offsets 04h, 06h and

07h, respectively.)

IRCR1, IRCR2 and IRCR3

Infrared Module Control Registers 1, 2 and 3 for

UART2. (Logical device 5. IRCR1 is in bank 4, off-

set 02h; IRCR2 is in bank 5, offset 04h; IRCR3 is in

bank 6, offset 00h.)

IrDA

Infrared Data Association.

IrDA-2 mode

In this mode, the part provides the Infrared Data

Association standard compliant interface.

IRQ

Interrupt Request.

IRRXDC

Infrared Receiver Demodulator Control register for

UART2. (Logical device 5, bank 7, offset 00h.)

IRTXMC

Infrared Transmitter Modulator Control register for

UART2. (Logical device 5, bank 7, offset 01h.)

ISA

Industry Standard Architecture for the PC bus.

LCR

Line Control Register for UART1 (logical device 6,

offset 03h) and for UART2 when enabled, i.e.,

when bit 7 of this register is 0 (logical device 5, all

banks, offset 03h).

Legacy

Usually refers to older devices or systems that are

not Plug and Play compatible.

Legacy Mode

In this mode, the interrupts and the base addresses

of the FDC, UARTs, KBC, RTC and the parallel

port of the part are conﬁgured as in earlier Su-

perI/O chips.

LFSR

The Linear Feedback Shift Register. In Plug and

Play mode, this register is used to prepare the chip

for operation in Plug and Play (PnP) mode.

LSB

Least Signiﬁcant Byte or Bit.

LSR

Line Status Register for UART1 (logical device 6,

offset 05h) and for UART2 in Non-Extended modes

only (logical device 5, bank 0, offset 05h).

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