PC97307 datasheet(174/218 Pages) NSC

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Power Management (Logical Device 8)

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Bits 6-3 - Reserved

Reserved.

Bit 7 - GPIO Ports Function Enable

0 - GPIO Ports 1 and 2 are inactive (disabled). Reads

and writes are ignored; registers and pins are

maintained. Bit 0 of the Activate register (index

30h) of the GPIO Ports logical device is ignored.

(Default)

1 - GPIO Ports 1 and 2 are active (enabled) when bit 0

of the Activate register (index 30h) of the GPIO

Ports logical device is set.

9.2.5

Power Management Control 1 Register (PMC1),

Index 02h

Hardware resets this read/write register to 00h.

A set bit puts the signals of the corresponding inactive logi-

cal device in TRI-STATE (except IRQ and DMA pins) re-

gardless of the value of bit 0 of the corresponding logical

device register at index F0h.

A cleared bit has no effect. In this case, the TRI-STATE sta-

tus of signals is controlled by bit 0 of the corresponding log-

ical device register at index F0h.

This is an OR function between PMC1 and the register at in-

dex F0h of the corresponding logical device.

FIGURE 9-5. PMC1 Register Bitmap

Bits 2-0 - Reserved

These bits are reserved.

Bit 3 - FDC TRI-STATE Control

0 - No effect. TRI-STATE controlled by bit 0 of the Su-

perI/O FDC Conﬁguration register. (Default)

See Section 2.6.1 on page 36.

1 - FDC signals are in TRI-STATE.

Bit 4 - Parallel Port TRI-STATE Control

0 - No effect. TRI-STATE controlled by bit 0 of the Su-

perI/O Parallel Port Conﬁguration register. (Default)

See Section 2.7.1 on page 37.

1 - Parallel Port signals are in TRI-STATE.

Bit 5 - UART2 and Infrared TRI-STATE Control

0 - No effect. TRI-STATE controlled by bit 0 of the Su-

perI/O UART2 Conﬁguration register. (Default)

See Section 2.8.1 on page 38.

1 - UART2 signals are in TRI-STATE.

FDC TRI-STATE Control

76543210

Reset

Required

Index 02h

Power Management

Control 1 Register

Parallel Port TRI-STATE Control

UART2 and Infrared TRI-STATE Control

Reserved

UART1 TRI-STATE Control

(PMC1)

Bit 6 - UART1 TRI-STATE Control

0 - No effect. TRI-STATE controlled by bit 0 of the Su-

perI/O UART1 Conﬁguration register. (Default)

See Section 2.9.1 on page 38.

1 - UART1 signals are in TRI-STATE.

Bit 7 - Reserved

Reserved.

9.2.6

Power Management Control 2 Register (PMC2),

Index 03h

Hardware resets this read/write register according to the

CFG2 and CFG3 strap pins, the status of the multiplier clock

and the hardware configuration. See Table 2-2 on page 25

and the description of the bits in this register.

FIGURE 9-6. PMC2 Register Bitmap

Bits 1,0 - SuperI/O Clock Source

Bit 0 is the Least Significant Bit (LSB).

00 - The 24 MHz clock is fed via the X1 pin.

01 - Reserved.

10 - The 48 MHz clock is fed via the X1 pin.

11 - The clock source is the on-chip clock multiplier.

Bit 2 - Clock Multiplier Enable

0 - On-chip clock multiplier is disabled.

1 - On-chip clock multiplier is enabled.

Bits 6-3 - Reserved

These bits are reserved.

Bit 7 - Valid Multiplier Clock Status

This bit is read only.

0 - On-chip clock (clock multiplier output) is frozen.

1 - On-chip clock (clock multiplier output) is stable and

toggling.

SuperI/O Clock Source

76543210

Reset

Required

Index 03h

Power Management

Control 2 Register

Clock Multiplier Enable

Reserved

Valid Multiplier Clock Status

(PMC2)

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