PC97307 datasheet(173/218 Pages) NSC

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173

Power Management (Logical Device 8)

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9.2.2

Power Management Data Register,

Base Address + 01h

This read/write register contains the data in the register

pointed to by the Power Management Index register at the

base address. See Figure 9-2.

FIGURE 9-2. Power Management Data Register

Bitmap

9.2.3

Function Enable Register 1 (FER1), Index 00h

Hardware resets this read/write register to FFh.

A set bit enables activation of the corresponding logical de-

vice via its Active register at index 30h.

A cleared bit disables the corresponding logical device re-

gardless of the value in its Active register. Bit 0 of the Active

ing FER1 bit is cleared. See Figure 9-3.

FIGURE 9-3. FER1 Register Bitmap

Bit 0 - KBC Function Enable

0 - Disabled.

1 - Enabled. (Default)

Bit 1 - Reserved

Reserved.

Bit 2 - RTC Function Enable

0 - Disabled.

1 - Enabled. (Default)

Data in the Indicated Power

76543210

Reset

Required

Base Address

Power Management

Management Register

Data Register,

+ 01h

KBC Function Enable

76543210

Reset

Required

Index 00h

Function Enable

UART2 and Infrared Function Enable

Reserved

RTC Function Enable

FDC Function Enable

Parallel Port Function Enable

UART1 Function Enable

Reserved

Bit 3 - FDC Function Enable

0 - Disabled.

1 - Enabled. (Default)

Bit 4 - Parallel Port Function Enable

0 - Disabled. (Default).

1 - Enabled.

Bit 5 - UART2 and Infrared Function Enable

0 - Disabled. (Default).

1 - Enabled.

Bit 6 - UART1 Function Enable

0 - Disabled. (Default)

1 - Enabled.

Bit 7 - Reserved

Reserved.

9.2.4

Function Enable Register 2 (FER2), Index 01h

Hardware resets this read/write register to FFh.

FIGURE 9-4. FER2 Register Bitmap

Bit 0 - Programmable CS0 Function Enable

See CS0 Configuration 0 register in Section 2.10.3 on

page 39.

0 - CS0 is disabled.CS0 is not asserted; CS0 conﬁgu-

ration and base address registers are maintained.

1 - CS0 is enabled. (Default)

Bit 1 - Programmable CS1 Function Enable

See CS1 Configuration 1 register in Section 2.10.7 on

page 40.

0 - CS1 is disabled.CS1 signal is not asserted, CS1

conﬁguration and base address registers are main-

tained.

1 - CS1 is enabled. (Default)

Bit 2 - Programmable CS2 Function Enable

See CS2 Configuration 2 register in Section 2.10.11 on

page 40.

0 - CS2 is disabled.The CS2 signal is not asserted,

CS2 conﬁguration and base address registers are

maintained.

1 - CS2 is enabled. (Default)

Programmable CS0 Enable

76543210

Reset

Required

Index 01h

Function Enable

Programmable CS1 Enable

Programmable CS2 Enable

Reserved

GPIO Ports Function Enable

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