PC97307 datasheet(164/218 Pages) NSC

164 / 218 page

164

UART1 and UART2 (with IR) (Logical Devices 5 and 6)

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If ID0/IRSL0/IRXX2 is programmed as an output

(IRSL0_DS = 1), then:

— If AMCFG (bit 7 of IRCFG4) is set to 1, this bit drives

the ID0/IRSL0/IRRX2 pin when Sharp-IR mode is

selected.

— If AMCFG is 0, this bit will drive the ID0/IRSL0/IRRX2

pin, regardless of the selected mode.

Upon read, this bit returns the value previously written.

Bits 2-1 - Transceiver Identiﬁcation/Control Bits 2-1

(IRIC2-1)

The function of these bits depends on whether the

ID/IRSL(2-1) pins are programmed as inputs or outputs.

If ID/IRSL(2-1) are programmed as input (IRSL21_DS =

0) then:

Upon read, these bits return the logic level of the pins

(allowing external devices to identify themselves).

Data written to these bit positions will be ignored.

If ID/IRSL(2-1) are programmed as output (IRSL21_DS = 1)

then:

If AMCFG (bit 7 of IRCFG4) is set to 1, these bits drive

the ID/IRSL(2-1) pins when Sharp-IR mode is selected.

If AMCFG is 0, these bits will drive the ID/IRSL(2-1)pins,

regardless of the selected mode.

Upon read, these bits return the values previously written.

Bit 3 - Transceiver identiﬁcation (IRID3)

Upon read, this bit returns the logic level of the ID3 pin.

Data written to this bit position is ignored.

Bits 6-4 - SIR Mode Transceiver Conﬁguration (SIRC(2-0))

These bits will drive the ID/IRSL(2-0) pins when AMCFG

(bit 7 of IRCFG4) is 1 and SIR mode is selected. They

are unused when AMCFG is 0 or when the ID/IRSL (2-

0) pins are programmed as inputs. SIRC0 is also un-

used when the IRSL0_DS bit in IRCFG4 is 0.

Upon read, these bits return the values previously written.

Bit 7 - Special Transceiver Mode Selection (STRV_MS)

When this bit is set to 1, the IRTX output signal is forced

to active high and a timer is started.

The timer times out after 64

µsec, at which time the bit

is reset and the IRTX output signal becomes low again.

The timer is restarted every time a 1 is written to this bit.

Although it is possible to extend the period during which

IRTX remains high beyond 64

µsec, this should be

avoided to prevent damage to the transmitter LED.

Writing a zero to this bit has no effect.

7.17.6

Reserved Register, Bank 7, Offset 05h

7.17.7

Infrared Interface Configuration 3 Register

(IRCFG3), Bank 7, Offset 06h

This register sets the external transceiver configuration for

the low speed and high speed Consumer IR modes of op-

eration. Upon reset, the content of this register is 00h.

FIGURE 7-39. IRCFG3 Register Bitmap

Bits 2-0 - Consumer-IR Mode Transceiver

Conﬁguration, Low-Speed (RCLC)

These bits drive the ID/IRSL(2-0) pins when AMCFG is 1

and Consumer-IR mode with 30-56 KHz receiver carrier

frequency is selected. They are unused when AMCFG is 0

or when the ID/IRSL(2-0) pins are programmed as inputs.

Upon read, these bits return the values previously written.

Bit 3 - Reserved

Read/Write 0.

Bits 6-4 - Consumer-IR Mode Transceiver

Conﬁguration, High-Speed (RCHC)

These bits drive the IRSL(2-0) pins when AMCFG (bit 7

of IRCFG4) is 1 and Consumer-IR mode with 400-480

KHz receiver carrier frequency is selected. They are un-

used when AMCFG is 0 or when the ID/IRSL(2-0) pins

are programmed as inputs.

Upon read, these bits return the values previously written.

Bit 7 - Reserved

Read/Write 0.

7.17.8

Infrared Interface Configuration Register 4

(IRCFG4), Bank 7, Offset 07h

This register configures the receiver data path and enables

the automatic selection of the configuration pins.

After reset, this register contains 00h.

FIGURE 7-40. IRCFG4 Register Bitmap

76543210

Reset

Required

Infrared Configuration

(IRCFG3)

Bank 7,

RCLC(2-0)

RCHC(2-0)

Reserved

Offset 06h

76543210

Reset

Required

Infrared Configuration

(IRCFG4)

Bank 7,

Reserved

RXINV

IRSL0_DS

Reserved

AMCFG

Reserved

IRSL21_DS

Offset 07h

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