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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DM9102AT датащи(PDF) 18 Page - List of Unclassifed Manufacturers |
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DM9102AT датащи(HTML) 18 Page - List of Unclassifed Manufacturers |
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18 / 77 page  DM9102A Single Chip Fast Ethernet NIC controller 18 Final Version: DM9102A-DS-F03 August 28, 2000 Miscellaneous Function (xxxxxx0c - PCILT) 31 16 15 0 87 23 24 BIST Header Type Latency Timer Cache Line Size Built-In Self Test Header Type Latency Timer For The Bus Master Cache Line Size For Memory Read Bit Default Type Description 31:24 00h RO Built In Self Test ( 00h Means Not Implementation) 23:16 00h RO Header Type ( 00h Means single function with Predefined Header Type ) 15:8 00h RW Latency Timer For The Bus Master. The latency timer is guaranteed by the system and measured by clock cycles. When the FRAME# asserted at the beginning of a master period by the DM9102A, the value will be copied into a counter and start counting down. If the FRAME# is de-asserted prior to count expiration, this value is meaningless. When the count expires before GNT# is de-asserted, the master transaction will be terminated as soon as the GNT# is removed. While GNT# signal is removed and the counter is non-zero, the DM9102A will continue with its data transfers until the count expires. The system host will read MIN_GNT and MAX_LAT registers to determine the latency requirement for the device and then initialize the latency timer with an appropriate value. The reset value of Latency Timer is determined by BIOS. 7:0 00h RO Cache line Size For Memory Read Mode Selection ( 00h Means Not Implementation For Use) I/O Base Address (xxxxxx10 - PCIIO) 31 0 1 7 8 1 0000000 I/O Base Address I/O Base Address PCI I/O Range I/O or Memory Space Indicator |
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