DM9102AT datasheet(25/77 Pages) ETC

25 / 77 page

DM9102A

Single Chip Fast Ethernet NIC controller

Final

Version: DM9102A-DS-F03

August 28, 2000

Control and Status Registers (CR)

The DM9102A implements 16 control and status registers,

which can be accessed by the host. These CRs are double

long word aligned. All CRs are set to their default values by

hardware or software reset unless otherwise specified. All

Control and Status Registers with their definitions and offset

from IO or memory Base Address are shown below:

Description

Offset from CSR

Base Address

Default value

after reset

CR0

System Control Register

00H

FEC00000

CR1

Transmit Descriptor Poll Demand

08H

FFFFFFFF

CR2

Receive Descriptor Poll Demand

10H

FFFFFFFF

CR3

Receive Descriptor Base Address Register

18H

00000000

CR4

Transmit Descriptor Base Address Register

20H

00000000

CR5

Network Status Report Register

28H

FC000000

CR6

Network Operation Mode Register

30H

02040000

CR7

Interrupt Mask Register

38H

FFFE0000

CR8

Statistical Counter Register

40H

00000000

CR9

External Management Access Register

48H

044097FF

CR10

Programming ROM Address Register

50H

Unpredictable

CR11

General Purpose Timer Register

58H

FFFE0000

CR12

PHY Status Register

60H

FFFFFFXX

CR13

Sample Frame Access Register

68H

XXXXXX00

CR14

Sample Frame Data Register

70H

Unpredictable

CR15

Watchdog And Jabber Timer Register

78H

00000000H

Key to Default

In the register description that follows, the default column

takes the form:

Where

<Reset Value>:

Bit set to logic one

Bit set to logic zero

No default value

<Access Type>:

RO = Read only

RW = Read/Write

RW/C = Read/Write and Clear

WO = Write only

Reserved bits are shaded and should be written with 0.

Reserved bits are undefined on read access.

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