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DM9102AT датащи(PDF) 12 Page - List of Unclassifed Manufacturers

номер детали DM9102AT
подробное описание детали  Single Chip Fast Ethernet NIC controller
PDF  77 Pages
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производитель  ETC [List of Unclassifed Manufacturers]
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DM9102AT датащи(HTML) 12 Page - List of Unclassifed Manufacturers

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DM9102A
Single Chip Fast Ethernet NIC controller
12
Final
Version: DM9102A-DS-F03
August 28, 2000
90
SPEED10#
/ LINK#
O
LED output pin, active low
mode 0 = 10Mbps LED
mode 1 = Link LED
Network Interface
Pin No.
128QFP/128TQFP
Pin Name
I/O
Description
105,106
RXI+
RX-
I
100M/10Mbps differential input pair.
These two pins are differential receive input pair for
100BASE-TX and 10BASE-T. They are capable of receiving
100BASE-TX MLT-3 or 10BASE-T Manchester encoded
data.
109,110
TXO+
TXO-
O
100M/10Mbps differential output pair.
These two pins are differential output pair for 100BASE-TX
and 10BASE-T. This output pair provides controlled rise and
fall times designed to filter the transmitter output.
Miscellaneous Pins
Pin No.
128QFP/128TQFP
Pin Name
I/O
Description
36
CLOCKRUN#
I/O,
O/D
Clockrun#
The clockrun# signal is used by the system to pause or slow
down the PCI clock signal. It is used by the DM9102A to
enable or disable suspension of the PCI clock signal or restart
of the PCI clock. When the clockrun# signal is not used, this pin
should connected to an external pull-down resistor.
71
TEST2
I
TEST mode control 2
In normal operation, this pin is pulled-high.
75
TEST1
I
TEST mode control 1
In normal operation, this pin is pulled low.
95
WOL/CSTSCHG
O
Wake up signal/Card Status Change
This is multiplexed pin to provide Wake on LANsignal or Card
Status Change. In a PCI system, it is used as a WOL signal. In
a CardBus system, it is used as the Card Status Change
output signal and is asynchronous to the clock signal. It
indicates that a power management event has occurred in a
CardBus system. The DM9102A can assert this pin if it detects
link status change, or magic packet, or sample frame. The
default is “normal low, active high pulse”. DM9102A also
support High/Low and Pulse/Level options.
97
X2
O
Crystal feedback output pin used for crystal connection only.
Leave this pin open if oscillator is used.
98
X1/OSC
I
Crystal or Oscillator input. (25MHZ
²50ppm)
25MHz Oscillator or series-resonance, fundamental
frequency crystal.
102
BGRES
I
Bandgap Voltage Reference Resistor.



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