DM9102AT datasheet(53/77 Pages) ETC

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DM9102A

Single Chip Fast Ethernet NIC controller

Final

Version: DM9102A-DS-F03

August 28, 2000

Bit 1: FUE, FIFO Underrun Error

It is set to indicate the transmission aborted due to transmit

FIFO underrun condition.

Bit 0: DF, Deferred

It is set to indicate the frame is deferred before ready to

transmit.

TDES1: Transmit buffer control and buffer size

21 ~ 11

10 ~ 0

E D

FMB1 SETF CAD

///

C E

PD FMB0

Buffer Length

Bit 31: CI, Completion Interrupt

It is set to enable transmit interrupt after the present frame

has been transmitted. It is valid only when TDES1<30> is

set or when it is a setup frame.

Bit 30: ED, Ending Descriptor

It is set to indicate the pointed buffer contains the last

segment of a frame.

Bit 29: BD, Begin Descriptor

It is set to indicate the pointed buffer contains the first

segment of a frame.

Bit 28: FMB1, Filtering Mode Bit 1

This bit is used with FMB0 to indicate the filtering type when

the present frame is a setup frame.

Bit 27: SETF, Setup Frame

It is set to indicate the current frame is a setup frame.

Bit 26: CAD, CRC Append Disable

It is set to disable the CRC appending at the end of the

transmitted frame. Valid only when TDES1<29> is set.

Bit 24: CE, Chain Enable

Must be “1”.

Bit 23: PD, Padding Disable

This bit is set to disable the padding field for a packet shorter

than 64 bytes.

Bit 22: FMB0, Filtering Mode Bit 0

This bit is used with FMB1 to indicate the filtering type when

the present frame is a setup frame.

FMB1

FMB0

Filtering Type

Perfect Filtering

Hash Filtering

Inverse Filtering

Hash-Only Filtering.

Bit 10-0: Buffer 1 length

Indicates the size of buffer in Chain type structure.

TDES2: Buffer Starting Address indicates the physical starting address of buffer.

Buffer Address 1

TDES3: Address indicates the next descriptor starting address

Indicates the physical starting address of the chained descriptor under the Chain descriptor structure.

This address must be eight word alignment.

Buffer Address 2

Initialization Procedure

After hardware or software reset, transmit and receive

processes are placed in the state of STOP. The DM9102A

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