DM9102AT datasheet(54/77 Pages) ETC

54 / 77 page

DM9102A

Single Chip Fast Ethernet NIC controller

Final

Version: DM9102A-DS-F03

August 28, 2000

can accept the host commands to start operation. The

general procedure for initialization is described below:

(1) Read/write suitable values for the PCI configuration

registers.

(2) Write CR3 and CR4 to provide the starting address of

each descriptor list.

(3) Write CR0 to set global host bus operation parameters.

(4) Write CR7 to mask causes of unnecessary interrupt.

(5) Write CR6 to set global parameters and start both

receive and transmit processes. Receive and transmit

processes will enter the running state and attempt to acquire

descriptors from the respective descriptor lists.

(6) Wait for any interrupt.

Data Buffer Processing Algorithm

The data buffer process algorithm is based on the

cooperation of the host and the DM9102A. The host sets

CR3 (receive descriptor base address) and CR4 (transmit

descriptor base address) for the descriptor list initialization.

The DM9102A will start the data buffer transfer after the

descriptor polling and get the ownership. For detailed

processing procedure, please see below.

1. Receive Data Buffer Processing

The DM9102A always attempts to acquire an extra

descriptor in anticipation of the incoming frames. Any

incoming frame size covers a few buffer regions and

descriptors. The following conditions satisfy the descriptor

acquisition attempt:

When start/stop receive sets immediately after being placed

in the running state.

When the DM9102A begins writing frame data to a data

buffer pointed to by the current descriptor and the buffer

ends before the frame ends.

When the DM9102A completes the reception of a frame

and the current receiving descriptor is closed.

When receive process is suspended due to no free buffer for

the DM9102A and a new frame is received.

When receive polling demand is issued. After acquiring the

free descriptor, the DM9102A processes the incoming frame

and places it in the acquired descriptor's data buffer. When

whole the received frame data has been transferred, the

DM9102A will write the status information to the last

descriptor. The same process will repeat until it encounters a

descriptor flagged as being owned by the host. If this occurs,

receive process enters the suspended state and waits the

host to service.

Stop

State

Descriptor

Access

Datat

Transfer

Write

Status

Suspended

Start Receive Command Or

Receive Poll Command

Buffer Available

( OWN bit = 1 )

FIFO Threshold

Reached

Frame Fully

Received

Buffer not

Full

Receive Buffer

Unavailable

New Frame Coming Or

Receive Poll Command

Stop Receive Command or

Reset Command

Buffer Full

Receive Buffer Management State Transition

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