DM9102AT datasheet(30/77 Pages) ETC

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DM9102A

Single Chip Fast Ethernet NIC controller

Final

Version: DM9102A-DS-F03

August 28, 2000

This bit is set when the DM9102A fetches the next transmit descriptor that is still

owned by the host. Transmit process will be suspended until the transmit polling

command is set or auto-polling timer time-out.

TXPS

0,RW

Transmit Process Stopped

This bit is set to indicate transmit process enters the stopped state.

TXCI

0,RW

Transmit Complete Interrupt

This bit is set when a frame is fully transmitted and transmit status has been written to

descriptor (the TDES1<31> is also asserted). Transmit process is still running and

continues to fetch next descriptor.

7. Network Operation Mode Register (CR6)

987

Bit

Name

Default

Description

RXA

0,RW

Receive All

When set, all incoming packet will be received, regardless the destination address.

The address match is checked according to theCR6<7>, CR6<6>, CR6<4>,

CR6<2>, CR6<0>, and RDES0<30> will show this match.

NPFIFO

0,RW

Set to not purge RX FIFO if RX buffer unavailable

28:26

Reserved

000,RO

Must be Zero

Reserved

1,RO

Must be One

24:23

Reserved

00,RO

Must be Zero

TXTM

1,RW

Transmit Threshold Mode

When set, the transmit threshold mode is 10Mb/s. When reset, the threshold mode

is 100Mb/s. This bit is used together with CR6<15:14> to decide the exact

threshold level.

SFT

0,RW

Store and Forward Transmit

When set, the packet transmission from MAC will be started after a full frame has

been moved from the host memory to transmit FIFO. When reset, the packet

transmission’s start will depend on the threshold value specified in CR6<15:14>

STI

0,RW

Start Transmission Immediately

When this bit is set, the packet transmission fromMAC will be started immediately

after transmit FIFO’s threshold level reaches 16 bytes, regardless of the setting in

CR6<22> and CR6<15:14>. This mode will make transmit FIFO underrun

condition to happen more easily.

Reserved

0,RO

Reserved

External

MII_Mode

1,RW

1: Select external MII interface.

0: Select external SRL interface.

In external MII mode that the pins TEST1, TEST2, and CLOCKRUN# are forced to

low, the DM9102A bypasses internal PHY and uses external PHY, by setting this

bit properly.

See page 66 for details.

Reserved

0,RO

Reserved

1pkt

0,RW

One Packet Mode

When this bit is set, only one packet is stored at TX FIFO.

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