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DM9102AT датащи(PDF) 28 Page - List of Unclassifed Manufacturers

номер детали DM9102AT
подробное описание детали  Single Chip Fast Ethernet NIC controller
PDF  77 Pages
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производитель  ETC [List of Unclassifed Manufacturers]
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DM9102AT датащи(HTML) 28 Page - List of Unclassifed Manufacturers

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DM9102A
Single Chip Fast Ethernet NIC controller
28
Final
Version: DM9102A-DS-F03
August 28, 2000
5. Transmit Descriptor Base Address (CR4)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
Bit
Name
Default
Description
31:0
TDBA
00000000h,
RW
Transmit Descriptor Base Address
This register defines base address of transmit descriptor-chain. The transmit
descriptor- polling command after
CR4 is set will make DM9102A to fetch the descriptor at the Base-Address.
6. Network Status Report Register (CR5)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
987
6
54
3
2
1
0
Bit
Name
Default
Description
25:23
SBEB
000,RO
System Bus Error Bits
These bits are read only and used to indicate the type of system bus fetal error. Valid
only when System Bus Error is set. The mapping bits are shown below.
Bit25
Bit24
Bit23
Bus Error Type
0
0
0
Parity error
0
0
1
Master abort
0
1
0
Slave abort
0
1
1
Reserved
1
X
X
Reserved
22:20
TXPS
000,RO
Transmit Process State
These bits are read only and used to indicate the state of transmit process.
The mapping table is shown below.
Bit22 Bit21 Bit20
Process State
0
0
0
Transmit process stopped
0
0
1
Fetch transmit descriptor
0
1
0
Move Setup Frame from the host memory
0
1
1
Move data from host memory to transmit FIFO
1
0
0
Close descriptor by clearing owner bit of descriptor
1
0
1
Waiting end of transmit
1
1
0
Transmit end and Close descriptor by writing status
1
1
1
Transmit process suspend
19:17
RXPS
000,RO
Receive Process State
These bits are read only and used to indicate the state of receive process. The
mapping table is shown below.
Bit19 Bit18 Bit17
Process State
0
0
0
Receive process stopped
0
0
1
Fetch receive descriptor
0
1
0
Waiting for receive packet under buffer available
0
1
1
Move data from receive FIFO to host memory



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