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DM9102AT датащи(PDF) 27 Page - List of Unclassifed Manufacturers

номер детали DM9102AT
подробное описание детали  Single Chip Fast Ethernet NIC controller
PDF  77 Pages
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производитель  ETC [List of Unclassifed Manufacturers]
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DM9102AT датащи(HTML) 27 Page - List of Unclassifed Manufacturers

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DM9102A
Single Chip Fast Ethernet NIC controller
Final
27
Version: DM9102A-DS-F03
August 28, 2000
Bit
Name
Default
Description
0
SR
0,RW
Software Reset
When set, the DM9102A will make a internal reset cycle. All consequent action to
DM9102A2 should wait at least 32 PCI clock cycles to start and no necessary to
reset this bit.
2. Transmit Descriptor Poll Demand (CR1)
31
30
29 28 27 26 25 24 23 22 21 20 19 18
17
16
15
14
13 12
11 10
98
7
6
5
4
3
2
1
0
Bit
Name
Default
Description
31:0
TDP
FFFFFFFFh
,WO
Transmit Descriptor Polling Command
Writing any value to this port will force DM9102A to poll the transmit descriptor. If
the acting descriptor is not available, transmit process will return to suspend state.
If the descriptor shows buffer available, transmit process will begin the data
transfer.
3. Receive Descriptor Poll Demand (CR2)
31
30
29 28 27 26 25 24 23 22 21 20 19 18
17
16
15
14
13 12
11 10
98
7
6
5
4
3
2
1
0
Bit
Name
Default
Description
31:0
RDP
FFFFFFFFh
,WO
Receive Descriptor Polling Command
Writing any value to this port will force DM9102A to poll the receive descriptor. If the
acting descriptor is not available, receive process will return to suspend state. If the
descriptor shows buffer available, receive process will begin the data transfer.
4. Receive Descriptor Base Address (CR3)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
Bit
Name
Default
Description
31:0
RDBA
00000000h
,RW
Receive Descriptor Base Address
This register defines base address of receive descriptor-chain. The receive
descriptor- polling command after CR3 is set will make DM9102A to fetch the
descriptor at the Base-Address.



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