DM9102AT datasheet(16/77 Pages) ETC

16 / 77 page

DM9102A

Single Chip Fast Ethernet NIC controller

Final

Version: DM9102A-DS-F03

August 28, 2000

Bit

Default

Type

Description

R/C

Detected Parity Error

The DM9102A samples the AD[0:31], C/BE[0:3]#, and the PAR signal to

check parity and to set parity errors. Inslave mode, the parity check falls

on command phase and data valid phase (IRDY# and TRDY# both

active). While in master mode, the DM9102A will check during each data

phase of a memory read cycle for a parity error During a memory write

cycle, if an error occurs, the PERR# signal will be driven by the target. This

bit is set by the DM9102A and cleared by writing "1". There is no effect by

writing "0".

R/C

Signal For System Error

This bit is set when the SERR# signal is driven by the DM9102A. This

system error occurs when an address parity is detected under the

condition that bit 8 and bit 6 in command register below are set.

R/C

Master Abort Detected

This bit is set when the DM9102A terminates a master cycle with the

master-abort bus transaction.

R/C

Target Abort Detected

This bit is set when the DM9102A terminates a master cycle due to a

target-abort signal from other targets.

R/C

Send Target Abort (0 For No Implementation)

The DM9102A will never assert the target-abort sequence.

26:25

R/C

DEVSEL Timing (01 Select Medium Timing)

Medium timing of DEVSEL# means the DM9102A will assert DEVSEL#

signal two clocks after FRAME# is sample “asserted.”

R/C

Data Parity Error Detected

This bit will take effect only when operating as a master and when a Parity

Error Response Bit in command configuration register is set. It is set under

two conditions:

(i) PERR# asserted by the DM9102A in memory data read error, (ii)

PERR# sent from the target due to memory data write error.

Slave mode Fast Back-To-Back Capable (0 For Not Support)

This bit is always reads "1" to indicate that the DM9102A is capable of

accepting fast back-to-back transaction as aslave mode device.

User-Definable-Feature Supported (0 For Not Support)

66 MHz Capable (0 For No Capability)

New Capabilities (1 For Good Capability)

This bit indicates whether this function implements a list of extended

capabilities such as PCI power management. When set this bit indicates

the presence of New Capabilities. A value of 0 means that this function

does not implement New Capabilities.

19:10

Reserved

Master Mode Fast Back-To-Back (0 For Not Support)

The DM9102A does not support master mode fast back-to-back capability

and will not generate fast back-to-back cycles.

SERR# Driver Enable/Disable

This bit controls the assertion of SERR# signal output. The SERR# output

will be asserted on detection of an address parity error and if both this bit

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