DM9102AT datasheet(57/77 Pages) ETC

57 / 77 page

DM9102A

Single Chip Fast Ethernet NIC controller

Final

Version: DM9102A-DS-F03

August 28, 2000

Serial Management Interface

The serial management interface uses a simple, two-wired

serial interface to obtain and control the status of PHY

management register set through an MDC and MDIO. The

Management Data Clock (MDC) is equipped with a

maximum clock rate of 2.5MHz, while Management Data

Input /Output (MDIO) works as a bi-directional, shared by up

to 32 devices.

In read/write operation, the management data frame is 64-

bit long start with 32 contiguous logic one bits (preamble)

synchronization clock cycles on MDC. The Start of Frame

Delimiter (SFD) is indicated by a <01> pattern followed by

the operation code (OP):<10> indicates Read operation and

<01> indicates Write operation. For read operation, a 2-bit

turnaround (TA) filing between Resistor Address field and

Data field is provided for MDIO toavoid contention. “Z”

stands for the state of high impedance. Following

turnaround time, a 16-bit data is read from or written onto

management registers.

Management Interface - Read Frame Structure

32 "1"s

0110

A 4

A 3

A 0

R 4

R 3

R 0

Idle

Preamble

SFD

Op Code

PHY Address

Turn Around

Data

Idle

Read

Write

MDC

MDIO Read

D15

D14

D 1

D 0

Management Interface - Write Frame Structure

32 "1"s

D15

D14

Idle

Preamble

SFD

Op Code

PHY Address

Turn Around

Data

Idle

Write

MDC

MDIO Write

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