UCS81003 datasheet(57/108 Pages) MICROCHIP

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 2014 Microchip Technology Inc.

DS20005334A-page 57

UCS81003

10.4.3

SWITCH CONFIGURATION

The contents of this register are retained in Sleep.

bit 2

EM_RESP: Leave Emulation Response - Enables the Dedicated Charger Emulation Cycle mode to

hold the DPOUT and DMOUT stimulus response after the UCS81003 has finished emulation using the

Legacy, BC1.2 DCP, or Custom charger emulation profiles (Note 2).

If a portable device begins drawing charging current while the UCS81003 is applying the BC1.2

DCP, Custom or any of the Legacy charger emulation profiles during the DCE Cycle, the last

response applied will be kept in place until a Removal Detection event occurs, the internal tem-

perature exceeds the TREG value, or emulation is restarted. In the case of the BC1.2 DCP or Leg-

acy 3 charger emulation profiles, this will be the short (RDCP_RES). In the case of the Legacy 1,

Legacy 2 or Legacy 4 - 7 profiles, this will be the DPOUT and DMOUT pin voltages. If a portable

device does not draw charging current, the DCE Cycle will behave normally.

The dedicated emulation circuitry will behave normally. It will remove the short condition when the

tEM_TIMEOUT timer has expired, regardless if the portable device has drawn charging current or

not.

bit 1-0

EM_RESET_TIME<1:0>: Determines the length of the tEM_RESET time (see Section 9.8.1 “Emulation

Reset”) as shown below. The value selected does not include discharge time; however, this value plus

discharge result in the actual reset time.

=50 ms

=75 ms

=125 ms

=175 ms

Note

If the EM_TO_DIS bit is set and the Legacy 2, Legacy 4 or Custom charger emulation profiles were accepted during the

DCE cycle, a removal is not detected. To avoid this issue, re-enable the emulation timeout after applying any test pro-

files and charging with the 'final' profile.

If the HSW_DCE bit is set, the high-speed switch will be closed regardless of the status of the EM_RESP bit. Leaving

the emulation response applied will not allow normal USB traffic. Therefore, prior to setting the HSW_DCE bit, this bit

should be cleared.

EMULATION CONFIGURATION REGISTER (ADDRESS 16H) (CONTINUED)

R/W-0

U-x

R/W-0

R/W-1

R/W-0

PIN_IGN

—

EM_EN_SET

M2_SET

M1_SET

S0_SET

PWR_ENS

LATCHS

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

PIN_IGN: Ignores the M1, M2, PWR_EN and EM_EN pin states when determining the Active mode

selection and power state.

The Active mode selection and power state will be set by the individual control bits and not by the

M1, M2, PWR_EN and EM_EN pin states. These pin states are ignored.

The Active mode selection and power state will be set by the OR’d combination of the M1, M2,

PWR_EN and EM_EN pin states and the corresponding bit states.

bit 6

Unimplemented

bit 5

EM_EN_SET: In conjunction with other controls, determines the Active mode that is selected (see

Section 9.2 “Active Mode Selection”) and power state (see Table 5-2). This bit is OR’d with the

EM_EN pin.

bit 4

M2_SET: In conjunction with other controls, determines the Active mode that is selected (see Section 9.2

“Active Mode Selection”) and power state (see Table 5-2). This bit is OR’d with the M2 pin.

bit 3

M1_SET: In conjunction with other controls, determines the Active mode that is selected (see Section 9.2

“Active Mode Selection”) and power state (see Table 5-2). This bit is OR’d with the M1 pin.

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