UCS81003 datasheet(42/108 Pages) MICROCHIP

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UCS81003

DS20005334A-page 42

 2014 Microchip Technology Inc.

9.8.1

EMULATION RESET

Prior to applying any of the charger emulation profiles,

the UCS81003 will perform an emulation reset. This

means that the UCS81003 resets the VBUS line by

disconnecting the port power switch and connecting

VBUS to ground via an internal 100 resistor for

tDISCHARGE time. The port power switch will be held

open for a time equal to tEM_RESET at which point the

port power switch will be closed and the VBUS voltage

applied. The DPOUT and DMOUT pins will be pulled low

using internal 15 k

 pull-down resistors.

9.8.2

EMULATION CYCLING

In Dedicated Charger Emulation Cycle mode, the

charger emulation profiles (if enabled) will be applied in

the following order:

Legacy 1

Legacy 2

Legacy 3

Legacy 4

Legacy 5

Legacy 6

Legacy 7

Custom (disabled by default). If the CS_FRST

configuration bit is set, then the Custom charger

emulation profile will be tested first and the order

will proceed as given.

If S0 = ’0’ and a portable device is not attached in DCE

Cycle mode, the UCS81003 will be cycling through

charger emulation profiles (by default). There is no

guarantee which charger emulation profile will be

applied first when a portable device attaches.

The UCS81003 will apply a charger emulation profile

until one of the following exit conditions occurs:

• Current greater than IBUS_CHG is detected flowing

out of VBUS at the respective emulation timeout

time. In this case, the profile is assumed to be

accepted and no other profiles will be applied.

• The respective emulation timeout (tEM_TIMEOUT)

time is reached without current that exceeds the

IBUS_CHG limit flowing out of VBUS (the emulation

timeout is enabled by default, see Section 10.4.2

“Emulation Configuration Register” and

rejected, and the UCS81003 will perform

emulation reset and apply the next profile, if there

is one.

Emulation timeouts can be programmed for each

charger

emulation

profile

(see

Section 10.11

“Preloaded

Emulation

Timeout

Configuration

Registers” and Register 10-35).

9.8.3

DCE CYCLE RETRY

If none of the charger emulation profiles cause a

charge current to be drawn, the UCS81003 will perform

emulation reset and cycle through the profiles again (if

the EM_RETRY bit is set (default - see Section 10.4.2

“Emulation

Configuration

The

UCS81003 will continue to cycle through the profiles as

long as charging current is not drawn and the PWR_EN

control is enabled. If the Emulation Retry is not

enabled, the UCS81003 will flag “No Handshake” and

end the DCE Cycle using Trip Current Limiting.

9.9

Current Limit Mode Associations

The UCS81003 will close the port power switch and

use the Current Limiting mode as shown in Table 9-2.

Note:

To help prevent possible damage to a

portable device, the DPOUT and DMOUT

pins have current limiting in place when

the emulation profiles are applied.

TABLE 9-2:

CURRENT LIMIT MODE OPTIONS

Active Mode

Current Limit Mode

(See Section 10.14 “Current Limiting Behavior

Configuration Registers”)

Data Pass-Through

Trip mode

BC1.2 SDP

Trip mode

BC1.2 CDP

CC mode if ILIM < 1.68A, otherwise, Trip mode

BC1.2 DCP

CC mode if ILIM < 1.68A, otherwise, Trip mode

DCE Cycle

During DCE Cycle when a charger emulation profile is

being applied and the emulation timeout is active

CC mode if ILIM < 1.68A, otherwise, Trip mode

Note 1:

As noted in the last three rows in Table 9-2, under those specific conditions with ILIM < 1.68A, it is the

relationship of ILIM and IBUS_R2MIN that determines the current limiting mode. In these cases, the value of

IBUS_R2MIN is determined by CS_R2_IMIN<2:0> bits 4-2 in the Custom Current Limiting Behavior

Configuration register - 51h (Register 10-49).

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