UCS81003 datasheet(50/108 Pages) MICROCHIP

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UCS81003

DS20005334A-page 50

 2014 Microchip Technology Inc.

INTERRUPT STATUS REGISTER (ADDRESS 10H)

R/W-0

R-0

ERR

DISCH_ERR

RESET

KEEP_OUT

TSD

OV_VOLT

BACK_V

OV_LIM

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

ERR: Indicates that an error was detected and the device has entered the Error state. Writing this bit to

a ‘0’ will clear the Error state and allows the device to be returned to the Active state. When written to

‘0’, all error conditions are checked. If all error conditions have been removed, the UCS81003 returns to

the Active state. This bit is set automatically by the UCS81003 when the Error state is entered. Regard-

less of the fault handling mechanism used, if any other bit is set in the Interrupt Status register (10h), the

device will not leave the Error state. (Note 1 and Note 2)

This bit is cleared automatically by the UCS81003 if the Auto-Recovery fault handling functionality is active

and no error conditions are detected. Likewise, this bit is cleared when the PWR_EN control is disabled.

One or more errors have been detected, and the UCS81003 has entered the Error state.

There are no errors detected.

bit 6

DISCH_ERR: Indicates that the UCS81003 was unable to discharge the VBUS node. This bit will be

cleared when read if the error condition has been removed or if the ERR bit is cleared. This bit will cause

the ALERT# pin to be asserted and the device to enter the Error state.

UCS81003 was unable to discharge the VBUS node.

=No VBUS discharge error.

bit 5

RESET: Indicates that the UCS81003 has just been reset and should be re-programmed. This bit will be

set at power up. This bit is cleared when read or when the PWR_EN control is toggled. The ALERT# pin

is not asserted when this bit is set. This data is retained in the Sleep state.

UCS81003 has just been reset

Reset did not occur.

bit 4

KEEP_OUT: Indicates that the V-I output on the VBUS pins has dropped below VBUS_MIN. This bit will be

cleared when read if the error condition has been removed or if the ERR bit is cleared. This bit will cause

the ALERT# pin to be asserted and the device to enter the Error state.

=VBUS < VBUS_MIN

=VBUS > VBUS_MIN

bit 3

TSD: Indicates that the internal temperature has exceeded TTSD threshold and the device has entered

the Error state. This bit will be cleared when read if the error condition has been removed or if the ERR

bit is cleared. This bit will cause the ALERT# pin to be asserted and the device to enter the Error state.

Internal temperature > TTSD

Internal temperature < TTSD

bit 2

OV_VOLT: Indicates that the VS voltage has exceeded the VS_OV threshold and the device has entered

the Error state. This bit will be cleared when read, if the error condition has been removed or if the ERR

bit is cleared. This bit will cause the ALERT# pin to be asserted and the device to enter the Error state.

=VS > VS_OV

=VS < VS_OV

bit 1

BACK_V: Indicates that the VBUS voltage has exceeded the VS or VDD voltages by more than 150 mV.

This bit will be cleared when read if the error condition has been removed or if the ERR bit is cleared.

This bit will cause the ALERT# pin to be asserted and the device to enter the Error state.

=VBUS >VS, or VBUS >VDD by more than 150 mV

=VBUS voltage has not exceeded the VS and VDD voltages by more than 150 mV

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